Commit graph

3210 commits

Author SHA1 Message Date
Yanyan Shen
07a5a3f5d9 riscv: Add memory fences and local ifence/sfence
Add memory fences.
Add local ifence and sfence which work on the calling
core only.
2019-10-10 17:22:06 +11:00
Yanyan Shen
8f7b168a53 riscv: Add SMP data
Add data for converting logical core ID to hart ID and vice verse.
2019-10-10 17:22:06 +11:00
Yanyan Shen
5a0d349845 riscv: Include header for SMP macros
Include header or SMP macros.
2019-10-10 17:22:06 +11:00
Yanyan Shen
99e9092b23 riscv: Set up the idle threads' per-core stacks
Use per-core stacks for idle thread stacks.
2019-10-10 17:22:06 +11:00
Yanyan Shen
1c53fea9d3 riscv: Add L1 cache line size and memory barrier
Add the L1 cache line size based on HiFive Unleashed.
2019-10-10 17:22:06 +11:00
Yanyan Shen
934080b7f5 riscv: Add IPI types and arch_pause() function
Add reschedule and call IPI types.
Add arch_pause() function.
2019-10-10 17:22:06 +11:00
Yanyan Shen
3505909fbe riscv: Add INTERRUPT_IPI_0 and INTERRUPT_IPI_1
Define constants for IPIs.
2019-10-10 17:22:06 +11:00
Yanyan Shen
e92b4e68b5 riscv: Add SMP functions
Add SMP functions for RISCV.
2019-10-10 17:22:06 +11:00
Yanyan Shen
a6c9dcf8a7 riscv: Use sscratch for per-core kernel stack
When SMP is enabled, the sscratch register is used to
contain the per-core kernel stack instead of the current
running thread. We get the current running thread from the
top of the kernel stack.
2019-10-10 17:22:06 +11:00
amrzar
a4d6bf850c SELFOUR-161: Merge Page_Remap with Page_Map
- Remove Remap function from seL4 API for arm, x86, riscv and the
respective invocation implementation.
- Update Map as replacement for Remap
- Update manual

This allows a change of rights if the frame being mapped is already
mapped in at the given vaddr. To map a page to a different address,
unmap it first.

Co-authored-by: Hesham Almatary <hesham.almatary@data61.csiro.au>
Co-authored-by: Anna Lyons <Anna.Lyons@data61.csiro.au>
Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
2019-10-10 15:54:23 +11:00
Kent McLeod
0f1f56d4ad ia32, boot: Create device frames for unused RAM
The ia32 kernel is supposed to pass through type 1 memory that is
outside of the kernel window as device untyped. In a previous refactor
this memory stopped getting created as untypeds. This behaviour is fixed
by pre-clamping the memory before being given to the free region list.
2019-10-08 15:01:02 +11:00
Anna Lyons
d09914aaa2 kernel: attempt direct switch on set prio
Prior to this commit the kernel would always trigger a full reschedule
on setPriority. This change allows the kernel to attempt a direct
switch, avoiding invoking the scheduler.

- Move location of setPriority call to after any cap deletion
  This makes the proof easier as setPriority now changes
  ksSchedulerAction, which is required to be ResumeCurrentThread or
  ChooseNewThread by the cap delete functions.
- Update to attempt direct switch on set prio.
2019-10-01 15:46:52 +10:00
Simon Shields
3e83f89990 x86: avoid -Waddress-of-packed-member
It's safe to take the address of this member, since it's the
first thing in a cacheline-aligned struct.
2019-09-26 15:34:26 +10:00
Curtis Millar
c25e5445fb mcs: Don't rollback time when not rescheduling
This allows ksCurTime to be monotonically increasing making proofs much
easier to construct.
2019-09-23 16:49:07 +10:00
Kent McLeod
8748d8ea5e seL4Config.cmake: Add FORCE to KernelSel4Arch
Without FORCE being added to `set` in declare_seL4_arch for
KernelSel4Arch, the set command doesn't seem to persist as the variable
must be already initialised in some cases. In this part of the script
processing, a platform has already been selected and is setting its seL4
arch and so using FORCE seems appropriate anyway.
2019-09-19 17:28:34 +10:00
Kent McLeod
8234026c1f aarch64: Move tpidrro_el0 from vcpu to tcb context
This register is visible to software executing at EL0 but not writeable.
Storing it in the VCPU context required custom save/restore handling as
it had to be explicitly handled when switching from a VCPU thread to a
non-VCPU thread so that it didn't become a channel. It is possible to
now update this register via seL4_TCB_WriteRegisters for software
executing at EL0.

This also fixes a potential bug where if a vcpu-thread is switched for a
non-vcpu-thread and then switched to a different vcpu-thread the
original vcpu-thread's copy of this register will get set to 0.
2019-09-19 11:39:14 +10:00
Kent McLeod
ef8b01390d KernelIRQReporting: Change reserved IRQ reporting
Reserved IRQ reporting would print on every received reserved IRQ. This
feature is supposed to report spurious interrupts, yet most cases
reserved IRQs are not spurious. We change the printing to only print if
the reserved IRQ was unhandled. The intention is to allow more app
configurations to leave this feature enabled in development builds.
2019-09-19 11:33:03 +10:00
Kent McLeod
b0f974c4a2 pc99,CMake: Move configs to x86 dir
These configs are also used by x86 files and this fixes an configuration
race condition where projects try set KernelIOMMU after platform
settings are configured and so KernelIOMMU doesn't result in a correct
value.
2019-09-19 11:33:01 +10:00
Kent McLeod
e93e45a123 CMake: Mark config options as advanced
This removes them from appearing in the CMake configuration cache and
being confusing.
2019-09-19 11:23:04 +10:00
Kent McLeod
af9a046031 CMake: Add KernelHardwareDebugAPIUnsupported
There are platforms/archs that don't support the Kernel Hardware Debug
API and they can now advertise that by setting
KernelHardwareDebugAPIUnsupported.
2019-09-19 11:23:04 +10:00
Kent McLeod
ed87dc35f2 gcc.cmake: Configure ccache in toolchain file
This should be a reasonable default option.
2019-09-19 11:23:01 +10:00
Damon Lee
123a0d844b armv8,CMake: Split generic timer, counter access
Instead of exporting the generic timer and counter access to userland in
one go, this commit splits it up into two different operations which
require two different build flags to be turned on. This is because the
timers expose a storage channel and allow threads to corrupt the
registers for each other.

Also move the config options to a better location and have them
depend on a more suitable config flag.
2019-09-18 14:51:07 +10:00
Anna Lyons
f02e59c59b armv8: expand generic timer user-level access
- allow the compare register to be set by user level (for both
  virtual and physical timer.
- allow the generic timer to be exported to EL1 as well when running
  seL4 as a hypervisor
2019-09-17 14:31:44 +10:00
Kent McLeod
58b6f3503e CMake: Add FindseL4.cmake module
This adds support for importing this project via `find_package(seL4)` if
the project exists in the CMAKE_MODULE_PATH.

sel4_import_kernel adds the kernel project to the current build
directory.

sel4_import_libsel4 adds libsel4 to the current build directory

sel4_configure_platform_settings imports seL4Config.cmake which
configures kernel configuration and toolchain settings for the target
platform.
2019-09-13 18:42:42 +10:00
Kent McLeod
d6bef3c533 cmake: Only include cmake files for selected arch
This prevents accidental declaration of properties or configurations
that are for the incorrect architecture selected. This was previously
required as the variables KernelWordSize and KernelArch were defined in
each arch specific cmake.config file. Now that they are defined in
advance it is possible to exclude the other imports.
2019-09-13 18:42:42 +10:00
Kent McLeod
b785b59930 cmake: Add SEL4_CONFIG_DEFAULT_ADVANCED variable
This directory-scoped varible is now used by config_option,
config_choice and config_string to set a created CMake cache variable as
advanced or not. An advanced variable is hidden by default in the CMake
configuration editors. Setting SEL4_CONFIG_DEFAULT_ADVANCED to ON will
cause variables to be advanced and not show up in the cache. Projects
can set this to limit the amount of options presented in the
config editor. Any cache variable can have this overridden by calling
mark_as_advanced(CLEAR config_name)
2019-09-13 18:42:42 +10:00
Kent McLeod
297d2b63da CMake: Invoke configuration files to build kernel
This leverages #!/usr/bin/env -S cmake -P to invoke a cmake
configuration file as a script that configures and builds a kernel in
the current directory with the configuration that was invoked. It is a
quick way for producing a kernel.elf or kernel_all_pp.c input file to
verification for a particular config.
2019-09-13 18:42:42 +10:00
Kent McLeod
d258af82ab CMake: Error if toolchain file changes
The toolchain file given to CMake is required to be immutable after
first build configuration. CMake caches certain build flags based on
this assumption. We now throw an error if the platform configuration
changes in a way that changes this toolchain file.
2019-09-13 18:42:42 +10:00
Kent McLeod
7d9297326b CMake: Possibly set toolchain file automatically
If CMAKE_TOOLCHAIN_FILE is unset in seL4Config.cmake then generate one
that selects the correct toolchain based on configured kernel arch
settings.

This means that initialising a build goes from:
`cmake -DCMAKE_TOOLCHAIN_FILE=gcc.cmake -DAARCH32=ON -G Ninja -C
../configs/ARM_verified.cmake ..`
to:
`cmake -G Ninja -C ../configs/ARM_verified.cmake ..`

gcc.cmake is modified to be used as an input to configure_file.
@KernelArch@ and other @@ arguments will be replaced with the
configuration settings. The file will still work if passed directly to
cmake via -DCMAKE_TOOLCHAIN_FILE=gcc.cmake without being templated.
2019-09-13 18:42:42 +10:00
Anna Lyons
7798b4767d aarch64: allow access to memory below physBase
On aarch64 physBase is the constant that points to the bottom of
physical memory (RAM).

Prior to this change the kernel window was mapped directly to physBase,
which is usually not a 0 paddr. As a consequence the kernel could not
access any memory below physBase.

This change fixes this issue by mapping the start of the kernel window
to 0 in the physical address space.

- add new constant PADDR_LOAD, the location of the kernel image in the
physical address space.
- add new constant PADDR_BASE, the start of the physical address space
(0).
- add new constant KERNEL_ELF_BASE, the location of the kernel image in
kernel virtual memory.

A consequence of this change is that on aarch64, the kernelBase constant
now points to the start of the kernel window in virtual memory, but
*not* to the start of the kernel image as these are now different.
2019-09-13 08:35:19 +10:00
Anna Lyons
3e685da663 aarch64: update fpsimd_HWCapTest for ARMv8.2
Prior to this commit this check would fail on ARMv8.2 and greater, as
having a bit set after this version does not imply that FPU/SIMD is not
supported.

For ARMv8.2 and above the values of the AdvSIMD/FP bits in
ID_AA64PFR0_EL1 are as follows:

- 0b1111 means FPU/SIMD is not supported.
- 0b0000 means FPU/SIMD is supported except for half-precision floating
point arithmetic.
- 0b0001 means FPU/SIMD is supported including half-precision floating
point arithmetic.
2019-09-11 13:46:46 +10:00
G. Branden Robinson
2b5c8d3f84 setup.py: depend on 'pyyaml', not 'pyaml'
In the pip namespace, 'pyaml' is "pretty-yaml", a YAML generator (but
not a YAML parser); 'pyyaml' (accessed with "import yaml"), a.k.a.
"PyYAML", is the YAML serialiser and reader we actually use.

Bump the minor version number per semantic versioning rules.  (One could
argue that we are "removing" pyaml (pretty-yaml) from our interface and
therefore a major version bump is required, but we weren't _actually_
using that module so I would argue that the introduction of 'pyyaml' is
the visible change.)

Thanks to Japheth Lim for identifying this issue.
2019-08-30 16:53:16 +10:00
G. Branden Robinson
fc251b5067 setup.py: add Python dependency on libarchive-c
The `shoehorn` tool in tools/seL4 (the sel4_tools repository) requires
this.

Bump minor version number per semantic versioning rules (interface
extension).  (0.3.1 instead of 0.3.0 because 0.3.0 saw the light of day
with an incorrect dependency on `libarchive` instead of `libarchive-c`.)
2019-08-28 15:54:10 +10:00
G. Branden Robinson
568f509b50 Revert "setup.py: add Python dep[] on libarchive"
This reverts commit a14264336c.

There are (at least) 3 namespaces relevant to Python module names:
Debian package names, PyPI module names, and the name of a module used
by actual Python language imports.  That's one more than my brain could
handle.  I wanted "libarchive-c" in setup.py instead of "libarchive".
2019-08-28 15:49:28 +10:00
Curtis Millar
9cd7958dbe hifive: Real time clock operates at 1MHz
The SiFive FU540-C000 runs mtime on the rtcclk which operates at 1MHz
from an external oscillator.
2019-08-27 10:46:13 +10:00
Curtis Millar
2f00d10f0e mcs: enable MCS for riscv
This allows an MCS kernel to be built on a RISC-V platform.
2019-08-27 10:46:13 +10:00
Curtis Millar
ccfd672039 mcs: Boot RISC-V with scheduling control & context
Make sure that when the kernel boots a scheduling control cap is created
and that the initial thread and idle thread are scheduled using correct
systemt time.
2019-08-27 10:46:13 +10:00
Curtis Millar
18219bbedf mcs: RISC-V uses 39-bit addressing in stuctures.bf
RISC-V uses 39-bit virtual addressing rather than 48 bits so the
'high' bits of a pointer can be 39 or fewer bits on RISCV rather than
48.
2019-08-27 10:46:13 +10:00
Curtis Millar
af34037edb trivial: spelling of the word 'canonical' 2019-08-27 10:46:13 +10:00
Curtis Millar
97782dcfb0 mcs: Update size constants for RISC-V
Update the notification size constant for the larger notification of MCS
and add the constant for the size of the reply object.
2019-08-27 10:46:13 +10:00
Curtis Millar
7adf81f6d7 mcs: fastpath_reply_recv reply argument for RISC-V
Add the reply argument to the fastpath_reply_recv call for RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
d869b3adb7 mcs: Timeout fault and reply for RISC-V
Add fault and reply for timeout faults on RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
f100d73f9c mcs: add mcs capability variants for riscv
When building for RISC-V, capabilities should include SchedControl and
SchedContext capabilities.
2019-08-27 10:46:13 +10:00
Curtis Millar
c45f2f0169 mcs: libsel4 for RISC-V
This uses the aarch64 code as a basis for implementing the full set of
new and updated libsel4 functions for RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
449dcd5038 mcs: Select additional registers for RISC-V
mcs requires an additional 2 registers for performing system calls to
pass information regarding the reply capability and the destination of a
nbsend/recv.
2019-08-27 10:46:13 +10:00
Curtis Millar
210eb59d9d mcs: Implement timer functions for RISC-V
Introduce the functions needed to read the time and set the timer for
MCS in RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
e19fddbb56 mcs: Remove timer init and reset from RISC-V
The timer init and reset are not needed to initialise the clock for MCS
in RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
1c4b6424d8 riscv: Fix rollover when reading time in 32-bit
If the time is being read in 32-bit mode it is read in two operations
between which the time can change. If the time causes the low bits to
roll over to 0 and the high bits to increment between reading the low
and high bits an incorrect time will be returned.

A check is added to ensure that an accurate time is returned.
2019-08-27 10:46:13 +10:00
Curtis Millar
557f8d4fb8 riscv: Relocate read time to header
Move the RISCV function to read the current time to the header file so
that it can be inlined for MCS.
2019-08-27 10:46:12 +10:00
G. Branden Robinson
a14264336c setup.py: add Python dependency on libarchive
The `shoehorn` tool in the tools/seL4 (the sel4_tools repository) will
require this in a future commit.

Bump minor version number per semantic versioning rules (interface
extension).
2019-08-26 14:31:18 +10:00