The C parser produces abbreviations for local variables that depend on
the variable type and the order they appear in the source.
The signature for `get_avail_p_reg` on RISCV has a different type for
`i` than every other function, which causes issues when `hardware.h` is
included early in `kernel_all.c_pp`. Changing the type to `word_t`
avoids these issues.
-Use debuglist for runqueues and filter idle and root thread.
-Refactor sendEPQueue.
-Add multicore support.
-Added TCB_COMMAND, kernel now does translation
depending on how it's configured.
Clang doesn't provide support for __attribute__((optimize ...)). There
are alternatives to provide the same functionality but due to how rarely
the kernel is compiled without optimisations, this can be added on
demand.
This change alters RISC-V fault handling to pass all non-VM faults as
user exceptions. As we cannot guarantee what the hardware will send us
in the scause register, we must handle all possible values.
It also makes fault handling more consistent with other architectures in
c_traps.c.
GCC accepts MCR/MRC instructions to modify fpu control registers. Clang
does not. VMSR/VMRS are instructions that the ARM specification suggests
to use when accessing fpu control registers.
We currently only support Sv39 on RV64. Sv39 has a cannonical address
range of -2^38 and 2^38-1. This means that bits 63-39 must be equal to
bit 38, or that we sign extend from bit 39 to 63 based on the value of
bit 38. It also means that we only have 39 bits of addressable space,
which limits our max untype size.
This change fixes support for instances where we have
multiple kernel devices in the same page, or kernel devices
which aren't at page-aligned addresses.
Also use seL4_UserTop to pick the right address to start
putting the kernel device pages.
Note that the auto-generated kernel_devices will differ slightly from
the ones present in the kernel until now. When devices have
registers that aren't page-aligned we now always set the appropriate
PPTR to be the start address of the device, while previously the PPTR
was sometimes page-aligned.
Specifically, this change to PPTRs affects:
- bcm2837 intc
- bcm2837 uart
- allwinnerA20 timer
doRemoteOp1Arg data1 and cpu arguments were switched,
which triggered a conditional statement preventing
the VM from exiting and handling a bound notification.
Change-Id: I019faeaf0c7d51ef7f6b2a2ffa83bea1cf76f811
* Also document the reason why the particular address for KS_LOG_PPTR was chosen.
This patch adds a pointer to the PD entry that sets the benchmark log frame.
Previously the kernel did not call vcpu_switch on the fastpath since the fastpath avoids
calling setVMRoot, so when sending an IPC message from a guest thread to a native thread,
if the IPC was small enough to go on the fastpath the kernel would fail to disable the
HYP traps and would treat the native thread like a guest thread.
aarch64 hyp mode only has support for 8 bit hardware ASIDs. We use the
same strategy used in aarch32 for hardware asids where we maintain a
pool of hwasids that seL4 ASIDs are allocated. The allocation is stored
in the last entry of top level paging structure. This commit
encapsulates this into the bitfield specification in the same way as
aarch32.
