Commit graph

179 commits

Author SHA1 Message Date
Qian Ge
1ef6e6c724 SMMU: supporting unbind context banks
Providing system calls on stream ID caps that unbinds its
context banks. Any future transaction using this stream ID
will result on faluts.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
2020-10-28 17:30:42 +11:00
Qian Ge
38ed1046e1 SMMU: supporting unassign vspace in context banks
Providing a system call that removes an assigned vspace root from its
context bank. This operation causes the context bank being disabled
as it does not have a valid vspace root after the unassignment.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
2020-10-28 17:30:42 +11:00
Qian Ge
b07ea94c0c SMMU: TLB invalidation system calls
Providing system calls for conducting TLB invalidation operations
on all TLB entries or entries in a context bank.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
2020-10-28 17:30:42 +11:00
Qian Ge
6e5911172c SMMU: binding stream ID to context banks
Providing system calls that binds context banks to stream IDs.
Once the stream ID is bound, the transaction using that SID is
enabled.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
2020-10-28 17:30:42 +11:00
Qian Ge
73e062bd45 SMMU: assigning vspace to context banks
Supporting user-level applications to assign vsapce root to context
banks through system calls. This commit also configures the context
bank according to stage 1 or stage 2 requirement.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
2020-10-28 17:30:42 +11:00
Qian Ge
0cf122a040 SMMU: system calls for creating SID and CB caps
Providing system calls on stream ID control cap and context bank
control cap for creating stream ID and context bank caps.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
2020-10-28 17:30:42 +11:00
Qian Ge
1a9756f65b SMMU: basic driver for init and probing
Introducing the driver in kernel for detecting SMMU features
and initialise the hardware.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
2020-10-28 17:30:42 +11:00
Gerwin Klein
5c1b81d9bb libsel4: fix license tags
These files should have been released under BSD-2-Clause in the first
place (as per parent LICENSE.md file).

Closes #245

Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
2020-09-04 20:30:01 +08:00
Kent McLeod
e1f6cf0ab0 Add 2 new benchmark utilization syscalls
- seL4_BenchmarkDumpAllThreadsUtilisation: Prints a JSON formatted
record of total and per-thread utilisation statistics about the system.
This currently includes a thread's total cycles scheduled, total number
of times scheduled, total cycles spent in the kernel and total number of
times entering the kernel and then totals of each for all threads on the
current core.
- seL4_BenchmarkResetAllThreadsUtilisation: Resets the current counts of
every user thread on the current core.

These syscalls are only available in a Debug build configuration as they
use a kernel debug list of all of the threads that exist for a given
node.

Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
2020-07-15 15:15:27 +10:00
Saer Debel
a221ee1ca8 Enabled IPC debug features under new config
Introduced a new config flag to enable
userError format strings to be written to the IPC buffer.
Another config bool has been introduced to toggle
printing the error out and this can also be set at runtime.

Signed-off-by: Saer Debel <saer.debel@data61.csiro.au>
2020-04-06 14:21:46 +10:00
Qian Ge
512a0200de replacing all ifndef with pargma once
All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.
2020-03-23 11:04:46 +11:00
Gerwin Klein
79da079239 Convert license tags to SPDX identifiers
This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.
2020-03-09 13:21:49 +08:00
Alison Felizzi
f795e7c0ec arm: New virtual PPI event fault type
This commit introduces a new fault type, seL4_Fault_VPPIEvent.

This change means the kernel can reserve PPI interrupts and virtualise
them via delivering the irq to the active vcpu through a
specific fault. This enables multiplexing PPI IRQs across multiple VCPUS
which requires correctly masking and unmasking the IRQ depending on
which VCPU is running.

A new VCPU invocation, seL4_ARM_VCPU_AckVPPI is also added for
acknowledging the handling of the IRQ. This takes an IRQ as a parameter
but will only accept IRQ numbers that are sent as VPPIEvent faults.

Co-authored-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
2020-02-20 11:40:59 +11:00
Siwei Zhuang
dadfb1b6f3 trivial: Bugfix, use the correct config macro
Use the correct config macro to enable code injection.
2020-02-12 12:36:57 +11:00
Luca(Wei) Chen
c06df578f2 ARM: Add support to flush L1 caches
Extend the existing seL4_BenchmarkFlushCaches without modifing the usage
of it. Will be used in sel4bench to measure the cold cache performance.
2020-02-11 11:23:04 +11:00
Jimmy Brush
b4e529ab2c trivial: arm: Improve object method docs 2020-01-06 16:14:02 +11:00
amrzar
a4d6bf850c SELFOUR-161: Merge Page_Remap with Page_Map
- Remove Remap function from seL4 API for arm, x86, riscv and the
respective invocation implementation.
- Update Map as replacement for Remap
- Update manual

This allows a change of rights if the frame being mapped is already
mapped in at the given vaddr. To map a page to a different address,
unmap it first.

Co-authored-by: Hesham Almatary <hesham.almatary@data61.csiro.au>
Co-authored-by: Anna Lyons <Anna.Lyons@data61.csiro.au>
Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
2019-10-10 15:54:23 +11:00
Curtis Millar
d869b3adb7 mcs: Timeout fault and reply for RISC-V
Add fault and reply for timeout faults on RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
c45f2f0169 mcs: libsel4 for RISC-V
This uses the aarch64 code as a basis for implementing the full set of
new and updated libsel4 functions for RISC-V.
2019-08-27 10:46:13 +10:00
Anna Lyons
a38e62f2f9 mcs: timeout exceptions
- Add seL4_TCB_SetTimeoutEndpoint
- implement timeout exceptions
2019-08-22 11:22:38 +10:00
Anna Lyons
554f812da3 mcs: scheduling context donation over ipc
After this commit, threads blocked on an endpoint can recieve a
scheduling context from the thread that wakes the blocked thread.
2019-08-22 11:22:37 +10:00
Sylvain Gauthier
49d3f2202d [SMP/Debug] New syscall to send arbitrary SGIs
Created a new syscall, seL4_DebugSendIPI for ARM to send arbitrary SGIs
(software generated interrupts) to arbitrary cores. As SGIs are
specifically PPIs (private interrupts), this syscall effectively allows
to trigger PPIs on arbitrary cores, for debug/testing purposes.
2019-07-19 16:35:57 +10:00
Curtis Millar
150916640e Add syscall for setting the current TLS register.
Some platforms and configurations do not allow user code to change the
value of the register used for TLS. On these architectures a syscall can
be used to allow the kernel to update the register on their behalf.

This does not immediately update the value in the user context on many
configurations as the values are only stored in the user context on a
context switch.
2019-07-01 11:17:49 +10:00
Curtis Millar
09d5e2454c Fix RISC-V registers to reflect calling convention 2019-07-01 10:46:46 +10:00
Curtis Millar
b6417f2150 Remove platform IPC buffer register.
This removes the assumption that each platform sotres the IPC buffer
address in a platform-specific register. The IPC buffer address is
instead stored in a thread-local variable in libsel4 which must be
initialised by the runtime.
2019-07-01 10:46:46 +10:00
Anna Lyons
90c49746a3 x86/ept: return correct MappingFailedLookupLevel
Prior to this change, seL4_MappingFailedLookupLevel() would retrun '22'
after any failed EPT mapping operation. This change fixes this to return
the correct amount of unresolved bits in the address.
2019-06-20 12:12:50 +10:00
Kent McLeod
4ce8f0a9f5 Add RISC-V IRQ invocations
We add support for seL4_IRQControlGet and seL4_IRQControlGetTrigger. If
a platform doesn't support setting the trigger, then
seL4_IRQControlGetTrigger will return an error. If the platform doesn't
have a PLIC driver, then it won't have any IRQs that can be requested.

Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
2019-06-18 10:22:47 +10:00
Sylvain Gauthier
84e6d4cdb1 Added IRQ routing to specific core for ARM
Add a new syscall, `seL4_IRQControl_GetTriggerCore`, to get a IRQHandler
with specific target core(s) and trigger method. Only available in SMP
mode.
2019-05-20 10:01:40 +10:00
Anna Lyons
7fc45c4ef1 style: set code width to 120 2019-03-19 14:05:44 +11:00
Anna Lyons
d0930f67de style: consistently attach return type
Add attach-return-type to astyle
2019-03-19 14:05:36 +11:00
Anna Lyons
761006e03b style: consistently align pointer with name
Run astyle with align-pointer=name
2019-03-19 14:04:54 +11:00
Anna Lyons
3d10ef0c4d style: correct parenthesis padding
Use astyle's unpad-paren to unpad all parentheses that are not included
by pad-header, pad-oper, and pad-comma.
2019-03-19 14:02:59 +11:00
Edward Pierzchalski
4ea62e5158 riscv: add remaining registers to user context.
The registers a7, s2-11, and t3-6 were missing from seL4_UserContext.
We also add these to frameRegisters and gpRegisters, which are used
to implement the TCB invocations for reading and writing these
registers.

Zero-length arrays aren't valid expressions or types in ISO C, so
to keep the c parser happy we need to either remove gpRegisters or
provide some contents for it.

In the past, frameRegisters and gpRegisters distinguished between
those registers preserved across a syscall and those that weren't.
TCB_CopyRegisters allows the caller to choose which set to copy.

Since we preserve all non-return registers, this distinction isn't
relevant anymore and there's no easy way to justify the members of
frameRegisters and gpRegisters.

We arbitrarily choose to put the 'last' register t6 in gpRegisters,
for consistency with the register list in registerset.h and with the
order that registers are restored.
2018-12-06 15:04:41 +11:00
Kofi Doku Atuah
fb854a7b14 Strongly type these interface arguments 2018-12-05 10:43:40 +11:00
Jimmy Brush
71a2c5384e
[libsel4] fix building with LibSel4FunctionAttributes
Correct exported functions that were still defined as 'static inline' to
use LIBSEL4_INLINE_FUNC so that they can be controlled by
LibSel4FunctionAttributes.

This is important to other languages that want to bind to the libsel4
static library instead of using the inline C functions.
2018-11-27 01:17:45 -05:00
Mitchell Buckley
f4f6b156e3 SELFOUR-1491: verification updates
- renamed an architecture label so that it begins with ARM.
- changed setIRQTrigger so that it takes a boolean value instead of an int.
- Arch_decodeIRQControlInvocation converts the second argument (trigger)
to a boolean immediately.
2018-09-19 12:06:35 +10:00
Anna Lyons
eb0553fa75 SELFOUR-1491: add seL4_IRQCOntrol_GetTrigger
Add a new invocation which allows an irq handler capability to be
obtained with a specific trigger method (edge or level). Obtaining
this capability modifies the GIC state.
2018-09-19 12:06:35 +10:00
Anna Lyons
5539b9e8b3 docs: s/depth of 32/depth equivalent to the wordsize 2018-09-19 12:06:35 +10:00
Anna Lyons
f17a80ed7f manual: remove duplicated word 2018-05-11 16:14:13 +10:00
Anna Lyons
996cb73d74 manual: correct vspace/pd usage for ARM invocations
Use vspace for the top-level paging structure and page directory specifically for page directories.
2018-05-11 16:14:11 +10:00
Anna Lyons
17b901d79f manual: clarify VSpace as top-level paging structure
This change updates the vspace chapter to separate the high-level concept of a VSpace from the
architectually defined objects. It also updates the various names for the vspace parameter to all be
vspace.
2018-05-11 16:14:09 +10:00
Anna Lyons
804fc54942 manual: update Page map documentation
- remove PD, PT references
- make clear that the middle level structures need mapping or an error is returned
2018-05-11 16:13:17 +10:00
Anna Lyons
ac01547562 manual: remove hard-coded PD, PT and Page invocations
- increases the maintainability of the docs
- move descriptions of methods to the API reference
- remove hardcoded invocations in manual

This commit removes the content completely from vspace.tex, as it is out of date and needs
restructuring. The next commit does the restructuring.
2018-05-11 16:13:08 +10:00
Anna Lyons
56abae43fb manual: remove hard-coded ASID invocations
- move documentation to API ref
- create tables pointing to the API ref for these objects
2018-05-11 16:13:06 +10:00
Adam Felizzi
fcff7ee2c4 manual: Updated Read VMCS description for docs
Changed \texttt{vmread} to `vmread`. Generated doxygen would strip
the latex command '\texttt', leaving just {vmread}.
2018-05-01 12:28:03 +10:00
Adam Felizzi
8fd604eb13 manual: Added <docref> XML Tag to Doxygen
Introduced a new Doxygen XML tag '<docref>'. The intention of
this tag is to indicate a section of text in the Doxygen XML that
will contain a reference to another section in the Manual e.g.
"See \autoref<sec:x>". As other generation formats aren't aware of
other chapters/sections in the manual, the <docref> encapsulation
allows it to omit the text from the output. The Latex generator
has been modified to continue parsing the 'docref' contents.
2018-05-01 12:28:03 +10:00
Adrian Danis
de42f82691 x86: Introduce IO port control caps
Changes the way IO ports work such that instead of 'minting' IO port caps down into new
IO port caps with smaller ranges new IO port ranges must be allocated centrally from
an IO port control cap. This mechanism acts in a very similar fashion as IRQ handler/control
capabilities and ensures that allocated IO ports do not overlap. Disallowing overlapping
IO ports is necessary to ensure the CDT remains valid as capabilities are deleted.
2018-04-24 14:04:46 +10:00
Anna Lyons
d3feb06cdd riscv: fix licenses
- add files from elsewhere to the license ignore
- s/D61_BSD/DATA61_BSD
2018-04-18 10:52:02 +10:00
Anna Lyons
74b220158a trivial: fix whitespace 2018-04-18 10:10:14 +10:00
Anna Lyons
aae12426e9 riscv: document API methods 2018-04-18 10:10:14 +10:00