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494 commits

Author SHA1 Message Date
Adrian Danis
2c49729da5 x86: Refactor tlb_bitmap to be mode generic 
Refactors the TLB bitmap code to be generic across ia32 and x86-64.
 2016-11-09 15:24:17 +11:00
Adrian Danis
9c91fc8f42 x86: Refactor generic x86 pte/pde manipulation 
Previously generic functions for manipulating page table and page
directory entries were placed in mode/structures.h. These are moved
to a mode/vspace.h instead so that they can use existing functions
defined in arch/vspace.h.

The x86_make_pde_mapping function is dropped in this move as it is
not used. Instead it is replaced with a function for creating an
empty mapping for whatever is the vspace root.
 2016-11-09 15:23:40 +11:00
amrzar
ffd0f34b39 Clean up x86KScurInterrupt: 
1. Remove the locking dependancy on the value of x86KScurInterrupt
2. Remove confusing set/unset of x86KScurInterrupt
 2016-11-09 14:22:04 +11:00
amrzar
b46e98c10e smp: solve bug in tlb_bitmap 
1. Missing loop counter when accessing to PD in 'tlb_bitmap_get'.
2. Missing 'TLBBITMAP_PD_INDEX' in 'TLBBITMAP_PD_MAKE_INDEX'. The index generated by 'TLBBITMAP_PD_MAKE_INDEX' should be valid in PD while the original one used to generate just 0, 1, etc. The correct index is '0 + TLBBITMAP_PD_INDEX', '1 + TLBBITMAP_PD_INDEX' and so on.
 2016-11-09 10:00:56 +11:00
Bamboo
846254be1f [STYLE_FIX] 2016-11-08 05:55:43 +00:00
Anna Lyons
c86669df43 x86: export tsc freq in bootinfo 
We read the frequency from the platform info MSR and export it to the
user for accurate timing (for platforms that support platform into)
 2016-11-08 14:46:18 +11:00
Adrian Danis
828a14d853 SELFOUR-222: Configure IRQ cnode size per platform 2016-11-08 11:48:31 +11:00
Adrian Danis
808f68e1be x64: Mode specific IPI definitions 2016-11-07 15:02:29 +11:00
Adrian Danis
9899c60c8b x86: Reduce number of irqs to 128 
On x86-64 the irq cnode will be larger than a page if there is more
than 128 irqs.
 2016-11-07 14:58:46 +11:00
Adrian Danis
1173e19aa6 x86: kernelSP only needed for ia32 2016-11-07 14:58:46 +11:00
Adrian Danis
6f908324f8 x64: Access core local state correctly 2016-11-07 14:58:46 +11:00
Adrian Danis
8b5ec01626 x86: Split IPIs into arch and mode portions 2016-11-07 14:53:46 +11:00
amrzar
44fc989cc5 Store remote FPU state 2016-11-07 14:41:25 +11:00
Bamboo
b90b715818 [STYLE_FIX] 2016-11-07 13:27:52 +11:00
Adrian Danis
61c1a4c4ff x64: Mode specific smp file 2016-11-07 12:18:43 +11:00
Adrian Danis
a726b4bea5 x86: Split CPU ID management into mode and general 
This moves getCurrentCPUIndex into a mode specific smp header, and
moves wrappers that use it into the generap smp header
 2016-11-07 11:46:08 +11:00
Adrian Danis
76b9441eee x86: Remove unused function 2016-11-07 11:44:57 +11:00
amrzar
056dbf811b SELFOUR-634: support for TLB and cache management 2016-11-07 10:55:05 +11:00
Anna Lyons
4a82597b7a trivial: change remoteTCBStall to take tcb 
Instead of cap_t. This allows the function to be used from other
functions that have the tcb pointer and not the cap.
 2016-11-07 10:37:17 +11:00
Adrian Danis
ab91c11a4f Merge pull request #459 in SEL4/sel4 from ~ADANIS/sel4:smmu to master 
* commit '858fa717c6a30fe1f0514c4ad8bbbe1003016864':
  tk1: Remove temporary SMMU memory mapping support
  arm: Remove lookup error message
  arm: Correctly mask SMMU PT addresses
  tk1: Correct SMMU PD and PT indexing
 2016-11-03 05:05:38 +00:00
Adrian Danis
a85472a951 x86: Always consider FPU owernship of threads core 
When checking if a thread is using the FPU or not we now check on that
threads core, under the assumption that if a thread migrates its FPU
state is explicitly (and not lazily) migrated.
 2016-11-03 10:18:24 +11:00
Adrian Danis
858fa717c6 tk1: Remove temporary SMMU memory mapping support 2016-11-02 15:12:56 +11:00
Adrian Danis
e3be5fa8e4 tk1: Correct SMMU PD and PT indexing 2016-11-02 15:12:56 +11:00
amrzar
3b19198bf4 Include vspace remote call support 2016-11-02 15:00:19 +11:00
amrzar
658eb090db Extend IPI for two function parameters 2016-11-02 13:47:29 +11:00
Thomas Sewell
03c71b63e1 SELFOUR-444: Preemptible zeroing for retype. 
Change to the order of operations and timing behaviour of
invokeUntyped_Retype. The Retype operation now zeroes the
entire range of the Untyped cap (if it is being used for
the first time) before installing any objects. This avoids
the need for long-running initialisation of large objects,
whose initial contents are always zero. The initial zeroing
phase is preemptible, and may take multiple timeslices to
complete.
 2016-11-01 17:05:36 +11:00
Bamboo
061f1b8d49 [STYLE_FIX] 2016-11-01 02:56:15 +00:00
amrzar
a228c492a6 Incuede TLBBitmap in PD to keep track of cores currently accessing this PD 2016-11-01 10:07:57 +11:00
Amirreza Zarrabi
b2295ea036 Merge pull request #434 in SEL4/sel4 from ~AZARRABI/sel4:sceduler_multicore to master 
* commit '25bb94372fe4afce072959af88c1afe9ff1c67d3':
  SELFOUR-635: support for TCB operations This will update TCB invocations to consider multicore environment, this may include: - adds the affinity invocation to transfer TCB between different cores and update TCB structure for core ID - checking the thread/core state before performing TCB operation, e.g. deleting the runnable TCB, etc
 2016-10-30 23:11:25 +00:00
Kent Mcleod
436b214ec6 Merge pull request #444 in SEL4/sel4 from ~KMCLEOD/sel4:pr to master 
* commit '66dfc2e786614a34c18ad2d7c20c04c69e589a97':
  Change ia32 to use fs register for IPC buffer
 2016-10-30 23:00:44 +00:00
amrzar
25bb94372f SELFOUR-635: support for TCB operations 
This will update TCB invocations to consider multicore environment, this may include:
- adds the affinity invocation to transfer TCB between different cores and update TCB structure for core ID
- checking the thread/core state before performing TCB operation, e.g. deleting the runnable TCB, etc
 2016-10-30 08:59:32 +11:00
Kent McLeod
66dfc2e786 Change ia32 to use fs register for IPC buffer 
gs register is used by gcc for TLS and the IPC buffer gets in the way
 2016-10-28 16:40:38 +11:00
Anna Lyons
40383a9882 Fix arm builds broken in 44ed6adb6 2016-10-28 16:16:04 +11:00
Anna Lyons
f0cb354755 Merge pull request #410 in SEL4/sel4 from ~ALYONS/sel4:cache to master 
* commit '44ed6adb616590a0f6ae8b0ad8c442afed625457':
  add seL4_BenchmarkFlushCaches() for arm and ia32
 2016-10-28 04:21:25 +00:00
Anna Lyons
44ed6adb61 add seL4_BenchmarkFlushCaches() for arm and ia32 
Available when CONFIG_ENABLE_BENCHMARKS is set, flushes caches for
running cold-cache benchmarks
 2016-10-28 15:09:03 +11:00
Adrian Danis
261d1f536c arm: Use #define for tcbArchCNodeEntries 
Using a #define allows the post processed C code to be identical
for the purposes of verification
 2016-10-28 13:58:22 +11:00
Adrian Danis
30f1d1fa7b x86: Comment #endif blocks for clarity 2016-10-28 13:51:21 +11:00
Bamboo
120a5e5496 [STYLE_FIX] 2016-10-28 01:34:31 +00:00
Adrian Danis
0012ea3e2e x86: fix FPU under SMP builds 2016-10-28 12:20:17 +11:00
Adrian Danis
da409659d0 x64: Match ASID changes on ia32 2016-10-28 12:14:16 +11:00
Adrian Danis
e83769322f x64: Update IO port cap type to match ia32 2016-10-28 12:13:42 +11:00
Adrian Danis
f8e6b4d9d6 x64: Guard vt-x that is not yet implemented 
These guards are needed because vt-x is not yet properly supported
in x86-64 builds. Once it is these guards can be removed again
 2016-10-28 12:12:46 +11:00
Adrian Danis
679d28c992 x64: Correct FPU handling code 2016-10-28 12:12:04 +11:00
Bamboo
6a86cbf5c7 [STYLE_FIX] 2016-10-27 05:34:49 +00:00
Adrian Danis
7fbde1bbcb SELFOUR-287: 32-bit vt-x implementation 
This is an implementation of vt-x for x86 kernels running in
ia32 mode.
 2016-10-27 16:20:30 +11:00
amrzar
f050e6a9c5 implement layout of ipi interrupt handling 2016-10-23 12:21:14 +11:00
Adrian Danis
ea47c2d4a4 Remove self include 2016-10-21 12:05:02 +11:00
Adrian Danis
ccb2e4b446 Remove circular include 
machine/hardware.h is already including machine/interrupt.h
 2016-10-21 12:05:02 +11:00
Adrian Danis
80dbdf5ed0 Remove unused include 2016-10-21 12:05:02 +11:00
Adrian Danis
7c08bc25e9 Remove include of basic_types 
arm/arch/types.h does not require any definitions from basic_types
(other than those from stdint, which is already directly included)
 2016-10-21 12:05:02 +11:00