Differing versions of gcc disagree on which combinations of mcpu and march are valid,
particularly around the armv7ve architecture. The solution here is to only set march
if it would not cause a conflict
Split up the bit specific code into new folders and added 64-bit
support. Also, changed the device register sizes to be based off of
PAGE_BITS instead of a hardcoded number.
TIMER_CLOCK_HZ is set to the default clock rate from the ATF,
which is the same for both AARCH32 and AARCH64.It may require changes
to the FSBL to work correctly.
The Zynq UltraScale+ MPSoC (PLAT zynqmp) is a Multi-Processor SOC
made by Xilinx that has a quad-core Cortex-A53, a dual-core Cortex-R5
and an FPGA.
This adds 32-bit, single-core support on the the Cortex-A53 cluster.
This renames the previous irq_t enum into a platform_irq_t enum and provides irq_t
as a 'well defined' uint8_t typedef. Having irq_t be an integer type, and not an enum,
is necessary for consistency with verification. As part of explicitly defining irq_t
as an unsigned integer type the definition of irqInvalid is changed to prevent sign
extension leading to unexpected invalid comparisons.
Restricting the value of TLS_BASE does not make sense as ultimately the user is prevented
from accessing the kernel region by virtue of protection levels and paging structures.
Whether the access is constructed by the user using a pointer (which in ia32 means an
implicit usage of `ds` selector) or through an explicit `fs` or `gs` selector does not
matter.
Using the `INTERNAL` attribute implied `FORCE` overriding any value the user may have set
for these. This was not the intention, and they should merely set a `CACHE` value if one
does not already exist.
Instead of explicitly depending on Kernel_C.thy prior to generating proofs, this removes
the dependency check and leaves isabelle to check the dependency upon import.
This provides documentation for kernel design of the x86 virtualisation, the additional
syscall and object invocations. The ARM design is not fully expanded.
Fixes an inconsistency between manual_label for the x86 AsidPool_Assign invocation
and its reference in the manual. This makes the x86 align with the ARM name.
An array is declared of size CONFIG_MAX_RMRR_ENTRIES, and if this is zero (such as
when the IOMMU is disabled), then it becomes a zero sized array, which is a GNU
C extension.
This matches the name with the L4V_ARCH variable in the verification tools and will
allow, as additional configurations are added, selecting the correct configuration
directly based on the configured L4V_ARCH from those tools.
Changes the name of paging structure entries to more clearly indicate the kind of object
they map to. Generally this is changing a `pde_small` to `pde_pt` to indicate that this
mapping refers to a page table, removing an inconsistency where `pde_large` indicated that
the mapping was for a large page. For the same reason the `ept_pde_4k` type is changed to
`ept_pde_pt` type to reflect what is present in the actual entry.
`pde_large` is left as 'large' and not explicitly given a size as code common between
ia32 and x86-64 manipulates these entities and 'large' is already a used abstraction
over the two potential page sizes so there is need to introduce a formal abstraction layer
and make the names in the structures more specific.
The purpose of this file is to track changes as they are made to the
kernel in order make writing release notes easier and tracking source or
binary level API breakages.
Nested structs with attributes are not understandable by the C parser. This change simply
moves the nested definitions into the global namespace (with suitable names).
Unlike other paging structure objects, each frame capability can hold a different mapping,
which should be unmapped. Previously we only performed an unmapping if we were deleting
the final frame capability, which meant if frame capabilities were deleting in the correct
order you could delete the final capability without first unmapping all usages of the
frame.
On the MCS kernel, Arch_migrateTCB is called in multiple places.
This commit moves the common code that is required when migrating a TCB
to a top level function to reduce boiler plate.
