Split up the bit specific code into new folders and added 64-bit
support. Also, changed the device register sizes to be based off of
PAGE_BITS instead of a hardcoded number.
TIMER_CLOCK_HZ is set to the default clock rate from the ATF,
which is the same for both AARCH32 and AARCH64.It may require changes
to the FSBL to work correctly.
The Zynq UltraScale+ MPSoC (PLAT zynqmp) is a Multi-Processor SOC
made by Xilinx that has a quad-core Cortex-A53, a dual-core Cortex-R5
and an FPGA.
This adds 32-bit, single-core support on the the Cortex-A53 cluster.
Restricting the value of TLS_BASE does not make sense as ultimately the user is prevented
from accessing the kernel region by virtue of protection levels and paging structures.
Whether the access is constructed by the user using a pointer (which in ia32 means an
implicit usage of `ds` selector) or through an explicit `fs` or `gs` selector does not
matter.
An array is declared of size CONFIG_MAX_RMRR_ENTRIES, and if this is zero (such as
when the IOMMU is disabled), then it becomes a zero sized array, which is a GNU
C extension.
Changes the name of paging structure entries to more clearly indicate the kind of object
they map to. Generally this is changing a `pde_small` to `pde_pt` to indicate that this
mapping refers to a page table, removing an inconsistency where `pde_large` indicated that
the mapping was for a large page. For the same reason the `ept_pde_4k` type is changed to
`ept_pde_pt` type to reflect what is present in the actual entry.
`pde_large` is left as 'large' and not explicitly given a size as code common between
ia32 and x86-64 manipulates these entities and 'large' is already a used abstraction
over the two potential page sizes so there is need to introduce a formal abstraction layer
and make the names in the structures more specific.
Unlike other paging structure objects, each frame capability can hold a different mapping,
which should be unmapped. Previously we only performed an unmapping if we were deleting
the final frame capability, which meant if frame capabilities were deleting in the correct
order you could delete the final capability without first unmapping all usages of the
frame.
On the MCS kernel, Arch_migrateTCB is called in multiple places.
This commit moves the common code that is required when migrating a TCB
to a top level function to reduce boiler plate.
The VT-x implementation is not going to be verified at the moment, and so the code for
it needs to be hidden from verification, which we do by #ifdef'ing it out if the VT-x
is not enabled. As a result the VT-x configuration depends on a non verification target
The IOMMU implementation is not going to be verified at the moment, and so the code for
it needs to be hidden from verification, which we do by #ifdef'ing it out if the IOMMU
is not enabled. As a result the IOMMU configuration depends on a non verification target
Changing the register used for the IPC buffer is useful as the standard TLS model for
aarch64 is to use tpidr_el0 for the thread pointer, which we are presently using
for the IPC buffer. This therefore paves the way for implementing proper TLS support
on aarch64.
Since we are not using tpidr_el0 for the IPC buffer we need to save/restore (or at
least clear) this register on thread switch to prevent it being a user channel. Saving
and restoring of it is achieved by ensuring CONFIG_IPC_BUF_TPIDRURW is not set, which
as we are no longer using this strategy this will be the case. To that end as aarch64
only has one IPC buffer strategy this commit makes the choice of IPC buffer strategy
dependeont on aarch32.
99.99% of the time this is what the user will want these set to in every thread, so
we might as well just set the sensible default here. Nothing stops the user overriding
this default later. This change will be unobservable to any existing (non broken) system
This commit implements lazy FP save/restore mechanism, required for user threads
when they use the FPU. The following caveats take place:
* Only support synchronous exceptions. No support for asynchronous ones.
* VFP opcodes are used instead of normal instructions to discard compiler warnings/errors.
* Support is limited to specific ARM subarchitectures we support and tested this commit on.
* Disable the FPU by default if users are not using it to avoid channels.
* FPU support is not verified yet.
* Will not work properly if using a VM that's running besides other VMs/threads that are using the FPU.
Previously if you wrote to TCB of the current thread and
changed the TLS_BASE this would not immediately take
affect, as the kernel only updates this register in
Arch_switchToThread. This change forces Arch_switchToThread
to get called, even if we would switch back to the original
thread.
Previously if you invoked the TCB of the current thread and
changed the IPC buffer frame this would not immediately take
affect, as the kernels view of the current IPC buffer is
updated in Arch_switchToThread. This change forces Arch_switchToThread
to get called, even if we would switch back to the original
thread.
ipi_send_mask is defined as:
void ipi_send_mask(irq_t ipi, word_t mask, bool_t isBlocking);
It expects an IRQ IPI number, not an interrupt number in the case of x86.
This commit:
1- Removes the confusion between IRQ and interrupt numbers by explicitly
converting IRQ to interrupt numbers in x86 implementation.
2- Makes the smp/ipi.c more generic to be shared with ARM, which only has
IRQ numbers for IPIs (send/receive).
