- Restart TCB from inside the lock if it is waiting for anything other than IRQ
- Only replace the TCB with idle thread if it is in ThreadState_RunningVM state
Also, this makes the design generic to be shared with arm.
This removes some duplicated constants and moves some constants into debug.h such that
they are visible without the user debugging API enabled. These constants are useful
for configuring other debugging/performance monitoring features.
This patch disables the debug register state save and restore on ARM-hyp,
such that Guest VMs can now interfere with one another and trigger
one another for certain limited scenarios. This will be undone later on.
* commit 'e8d3672c9a89c32f8d074d57cfe428fde839eb47':
SELFOUR-745: ARM/SMP - Add lock/unlock code to kernel entry/exit points
SELFOUR-744: ARM/SMP - Map kernel window and root task as cache-shareable
SELFOUR-744: ARM - preliminary booting of other cores
SELFOUR-744: Add utililty function to read MPIDR register (CPU ID)
ARM/Stack: Add utililty function to get seL4 top stack pointer from HW register
There is no 'object' backing an IO port capability, rather it represents the
authority to use an IO port range. The derived authority for ranges is checked
by `Arch_sameRegionAs`, but currently `Arch_sameObjectAs` always considers
two IO port caps to not be from the same object. Whilst this is true, it is
also true to say that all IO ports are from the same object (since there is
no object).
As it is easier to reason about IO port caps being from the same object, and
then restriction by region, this changes `Arch_sameObjectAs` to consider all
IO port caps to be from the same object.
`vcpu_switch` is used in `setVMRoot` to switch the active VCPU, or to enable/disable
certain virtualization if going to/from using a VCPU. When running the idle thread
we do not leave kernel mode and having a VCPU active or not is almost irrelevant,
except that interrupts are enabled and the VGIC can generate interrupts. Whilst the
VGIC should not generate an interrupt whilst the idle thread is running, this is
problematic for verification
This patch enables the hype-mode kernel to intercept non-secure PL0
debug exceptions. Since it uses the HDCR register to do this (and not the SDCR),
it consequentially has no effect on any secure-monitor that may be executing
alongside the hypmode kernel.
For native seL4-hyp user threads, when the CPU sees a need to raise a debug
exception that was taken from PL0 (user), it will naturally try to raise that
exception to PL1 (supervisor).
But since seL4 is in PL2 and not PL1, seL4 has not set up an exception vector
table (VBAR) for PL1. So when the CPU attempts to vector into the PL1 VBAR,
it just gets a data abort, which it then delivers to PL2.
This patch causes the PL2 seL4 hypervisor to directly catch the debug exception
straight from PL0 and process the debug exception directly, for native threads.
Guest VM VCPUs are unaffected by this change. Their debug exceptions are delivered
to the Guest VM's PL1 VBAR as per usual.
As things are now, the Guest VMs can modify the debug registers at will
from non-secure PL1, and the kernel does nothing to ensure that guest VM
debug coprocessor registers are preserved.
This is a preliminary patch that simply hooks into vcpu_save and saves the
CPU's debug coprocessor registers when saving VCPU state.
For restoring the debug registers on switching to a VCPU, we just re-use
restore_user_debug_context, which is already called in restore_user_context.
(Restore_user_context is called by c_handle_vcpu_fault()). Specifically,
we modify the used_breakpoints_bf so that restore_user_debug_context()
will always pop all the debug context.
This patch only covers the breakpoint and watchpoint registers,
and it doesn't cover the entire debug coprocessor, which is another
conversation.
The SDER (Secure Debug Enable Register) has two bits that control the enabling
of debug exceptions at PL0 for secure-world. They enable respectively,
invasive debugging and non-invasive debugging. We were indiscriminately
enabling both when we only needed to enable invasive debugging at PL0.
This patch disables non-invasive secure-PL0 debugging because it's not
needed.
Also add a comment for DBGAUTHSTATUS.
* commit '5253dca8b1e6a5cda3b6c7adce55f398ee3274fe':
SELFOUR-746: ARM/SMP - Reserve the first two SGI IDs for seL4 IPI
SELFOUR-746: ARM/GIC - Provide IPI support
SELFOUR-746: ARM/GIC - bank active_irq for each core
Similar to initIRQController(), cpu_initLocalIRQController() has to
be implemented for each platform. For those that are gonna support
SMP, it should be implemented proprely (if required), otherwise
it can be stubbed for single core implementations.
On 64-bit platforms physical address could be >2^32 offset from a virtual address. This
changes offsets to match the word size of the target architecture
In SMP context, init_cpu is meant to be called for each CPU, where
initialising private timer, user access and benchmarks (basically CCNT)
are per-CPU operations and involve per-CPU hardware
resources/interrupts.
