Commit graph

687 commits

Author SHA1 Message Date
amrzar
93cc22b289 smp: fix bugs when stalling remote core
- Restart TCB from inside the lock if it is waiting for anything other than IRQ
- Only replace the TCB with idle thread if it is in ThreadState_RunningVM state

Also, this makes the design generic to be shared with arm.
2017-03-30 09:46:43 +11:00
Adrian Danis
8f7f8502e7 SELFOUR-712: arm: enable user level PMU event counter on v7 2017-03-28 12:10:51 +11:00
Adrian Danis
c104c82f5a arm: Refactor constants from debug API
This removes some duplicated constants and moves some constants into debug.h such that
they are visible without the user debugging API enabled. These constants are useful
for configuring other debugging/performance monitoring features.
2017-03-28 12:10:31 +11:00
Kofi Doku Atuah
725d0dacfd SELFOUR-836: Disable debug context save/restore between VMs
This patch disables the debug register state save and restore on ARM-hyp,
such that Guest VMs can now interfere with one another and trigger
one another for certain limited scenarios. This will be undone later on.
2017-03-21 15:31:23 +11:00
Hesham Almatary
26c81b9ff4 x86: move pdpte_t to 64/mode and delete it for ia32 2017-03-17 09:50:52 +11:00
Hesham Almatary
2cd909b2e9 ia32: remove unsued ia32KSGlobalPDPT and PDPT defines 2017-03-17 09:50:52 +11:00
Anna Lyons
f42d63631b refactor: initialise common core state in one place 2017-03-16 11:15:04 +11:00
Bamboo
9601f0fdfe [STYLE_FIX] 2017-03-09 02:36:15 +00:00
Kent McLeod
adeb341f48 tk1: Add missing device regions 2017-03-09 12:40:56 +11:00
Hesham Almatary
e8d3672c9a SELFOUR-745: ARM/SMP - Add lock/unlock code to kernel entry/exit points 2017-03-08 09:31:32 +11:00
Hesham Almatary
d5bd84e00f SELFOUR-744: Add utililty function to read MPIDR register (CPU ID) 2017-03-06 15:00:11 +11:00
Hesham Almatary
33da2e0f37 ARM/Stack: Add utililty function to get seL4 top stack pointer from HW register 2017-03-06 15:00:11 +11:00
Adrian Danis
ccd9020b6a Pass tcb_t to sanitiseRegister instead of arch_tcb_t 2017-03-06 13:42:33 +11:00
Kofi Doku Atuah
f12f0477c0 Add PL0 debug-API support for hyp-mode kernel
This patch enables the hype-mode kernel to intercept non-secure PL0
debug exceptions. Since it uses the HDCR register to do this (and not the SDCR),
it consequentially has no effect on any secure-monitor that may be executing
alongside the hypmode kernel.

For native seL4-hyp user threads, when the CPU sees a need to raise a debug
exception that was taken from PL0 (user), it will naturally try to raise that
exception to PL1 (supervisor).

But since seL4 is in PL2 and not PL1, seL4 has not set up an exception vector
table (VBAR) for PL1. So when the CPU attempts to vector into the PL1 VBAR,
it just gets a data abort, which it then delivers to PL2.

This patch causes the PL2 seL4 hypervisor to directly catch the debug exception
straight from PL0 and process the debug exception directly, for native threads.

Guest VM VCPUs are unaffected by this change. Their debug exceptions are delivered
to the Guest VM's PL1 VBAR as per usual.
2017-03-01 10:49:27 +11:00
Kofi Doku Atuah
469bdd6156 ARM-HYP: Add support for save/restore of debug registers
As things are now, the Guest VMs can modify the debug registers at will
from non-secure PL1, and the kernel does nothing to ensure that guest VM
debug coprocessor registers are preserved.

This is a preliminary patch that simply hooks into vcpu_save and saves the
CPU's debug coprocessor registers when saving VCPU state.

For restoring the debug registers on switching to a VCPU, we just re-use
restore_user_debug_context, which is already called in restore_user_context.
(Restore_user_context is called by c_handle_vcpu_fault()). Specifically,
we modify the used_breakpoints_bf so that restore_user_debug_context()
will always pop all the debug context.

This patch only covers the breakpoint and watchpoint registers,
and it doesn't cover the entire debug coprocessor, which is another
conversation.
2017-03-01 10:23:29 +11:00
Hesham Almatary
ecb54e09e6 Merge pull request #708 in SEL4/sel4 from ~HALMATARY/sel4:SELFOUR-746 to master
* commit '5253dca8b1e6a5cda3b6c7adce55f398ee3274fe':
  SELFOUR-746: ARM/SMP - Reserve the first two SGI IDs for seL4 IPI
  SELFOUR-746: ARM/GIC - Provide IPI support
  SELFOUR-746: ARM/GIC - bank active_irq for each core
2017-03-01 10:07:46 +11:00
Hesham Almatary
bf9d02f3ca Merge pull request #709 in SEL4/sel4 from ~HALMATARY/sel4:ARM/IRQ to master
* commit 'b8f9dcac64603debc2d1e235f8032ee504cd4845':
  ARM/IRQ: add a function to initialise local IRQ controller for CPUs
2017-03-01 09:55:44 +11:00
Adrian Danis
256c30ae02 x86: Pass VBE information from multiboot through bootinfo 2017-02-28 16:35:50 +11:00
Hesham Almatary
5253dca8b1 SELFOUR-746: ARM/SMP - Reserve the first two SGI IDs for seL4 IPI 2017-02-28 15:56:27 +11:00
Hesham Almatary
b8f9dcac64 ARM/IRQ: add a function to initialise local IRQ controller for CPUs
Similar to initIRQController(), cpu_initLocalIRQController() has to
be implemented for each platform. For those that are gonna support
SMP, it should be implemented proprely (if required), otherwise
it can be stubbed for single core implementations.
2017-02-28 13:39:49 +11:00
Hesham Almatary
b95dec2f7b SELFOUR-746: ARM/GIC - Provide IPI support 2017-02-28 10:13:43 +11:00
Hesham Almatary
8f859a7d32 SELFOUR-746: ARM/GIC - bank active_irq for each core 2017-02-28 10:03:15 +11:00
Hesham Almatary
db15ec7c46 Merge pull request #704 in SEL4/sel4 from ~HALMATARY/sel4:ARMSMP3 to master
* commit '03c323c18ef5ecf82fa962bc9e441870e6ed290f':
  ARM/Boot: initialise private timer, user access and benchmark in CPU context
2017-02-28 09:47:42 +11:00
Adrian Danis
c43954252c Remove assumption on 32-bit memory offsets
On 64-bit platforms physical address could be >2^32 offset from a virtual address. This
changes offsets to match the word size of the target architecture
2017-02-28 08:28:01 +11:00
Bamboo
4d54476621 [STYLE_FIX] 2017-02-27 06:26:58 +00:00
Hesham Almatary
03c323c18e ARM/Boot: initialise private timer, user access and benchmark in CPU context
In SMP context, init_cpu is meant to be called for each CPU, where
initialising private timer, user access and benchmarks (basically CCNT)
are per-CPU operations and involve per-CPU hardware
resources/interrupts.
2017-02-27 15:05:21 +11:00
amrzar
dea3d9819d X64: add CONFIG_HAVE_FPU to autoconf.h 2017-02-27 14:25:08 +11:00
amrzar
8610061aa9 aarch64: FPU lazy context switch 2017-02-27 14:25:01 +11:00
amrzar
0707ae874b Move arch independent functions to generic files and HAVE_FPU config 2017-02-27 12:52:18 +11:00
amrzar
ae8f2c99d7 x86: move current active FPU owner to node state 2017-02-27 12:52:18 +11:00
amrzar
323e60a749 x86: define number of restore since switch as node state 2017-02-27 12:52:18 +11:00
amrzar
195e5a0db8 pcc99: move max restore config value to main Kconfig 2017-02-27 12:52:18 +11:00
Kent McLeod
325db51cb1 Fix type error in benchmark.h 2017-02-27 09:31:11 +11:00
Hesham Almatary
35e4811572 Verification: Guard getCurrentCPUIndex() with SMP #define 2017-02-23 11:44:42 +11:00
Hesham Almatary
f97d6f3d14 Merge pull request #683 in SEL4/sel4 from ~HALMATARY/sel4:ARMSMP to master
* commit 'c1407c55216deba425fe32079ca786d213c5509e':
  [SELFOUR-744]: Modify head.S to load stacks for each core and implement getCurrentCPUIndex
2017-02-23 11:23:11 +11:00
Adrian Danis
712efa63cb arm_hyp: Use an explicitly invalid PD when there is no user one
When the user has no PD in order to schedule them we must still set something as
the active PD, just so that they can then fault. Previously when hypervisor was
enabled `0` was at as the PD. This worked as platforms typically do not have
anything valid, and certainly nothing resembling a page directory, at physical
address 0. This assumption is not very clean and unknown physical addresses
should not be accessed, so this change adds an explicit PD that is empty that
can be switched to.
2017-02-22 17:23:09 +11:00
Adrian Danis
f8606c86ad Provide spec for CTZL
Provides a spec for the __builtin_ctzl function and changes existing
code to use this wrapper
2017-02-22 17:22:17 +11:00
Hesham Almatary
34fe58a334 Fix: add pdpt stuff removed from shared x86 code to x86_64 2017-02-22 15:20:15 +11:00
Adrian Danis
4632e77d85 Correctly indent license headers 2017-02-21 16:39:07 +11:00
Adrian Danis
eccaae51dc s/D61/DATA61/ in license headers for consistency 2017-02-21 16:38:51 +11:00
Hesham Almatary
bca46830e9 Merge pull request #420 in SEL4/sel4 from ~HALMATARY/sel4:x86RemovePAE to master
* commit '3e57e647e9a882fc7ba07329bcfe41ff87af5bdb':
  SELFOUR-501: x86 - Remove PAE support
2017-02-21 16:14:34 +11:00
Hesham Almatary
c1407c5521 [SELFOUR-744]: Modify head.S to load stacks for each core and implement getCurrentCPUIndex 2017-02-21 09:48:08 +11:00
Hesham Almatary
3e57e647e9 SELFOUR-501: x86 - Remove PAE support 2017-02-17 13:13:43 +11:00
Hesham Almatary
ba14b5fa7d Merge pull request #682 in SEL4/sel4 from ~HALMATARY/sel4:fixAARCH64 to master
* commit 'e0e49db0ece32af40cdcc5dd81d210078bf2b1d9':
  trivial: add place holder smp.h file for aarch64
2017-02-17 11:33:11 +11:00
Hesham Almatary
e0e49db0ec trivial: add place holder smp.h file for aarch64 2017-02-17 11:28:42 +11:00
Jack Suann
75ff2cd2e0 Merge pull request #677 in SEL4/sel4 from ~JSUANN/sel4:pendirq-sc to master
* commit '50995b4c5f5bfd88c0ae049966f58f5cdcd6d8df':
  Replace Arch_handleInterrupt with Arch_finaliseInterrupt
2017-02-17 11:20:17 +11:00
Bamboo
e45ee8b135 [STYLE_FIX] 2017-02-16 23:57:13 +00:00
Hesham Almatary
0ef7c693ce x86: define L1_CACHE_LINE_SIZE_BITS as with ARM 2017-02-16 15:28:05 +11:00
Hesham Almatary
67cdff7b68 SMP: Move/rename migrateTCB() arch tcb.c 2017-02-16 15:28:05 +11:00
Hesham Almatary
48d17e1f58 ARM/SMP: Prepare for ARM SMP adding stubs
Currently building ARM/SMP is broken. This commit:
1- Makes it possible to build ARM/SMP with stubs. Run-time SMP for ARM
DOES NOT WORK.
2- Can be a reference for future SMP targets to follow in order to
layout/add the minimal required files and functions needed to support SMP.
3- Builds for Sabre only. In order to support other platforms, ipi
interrupt ID should be defined in machine.h
2017-02-16 15:28:00 +11:00