This allows for arm headers to be generated for an arm platform
in include/plat/default that specifies the following:
- maxIRQ
- TIMER_CLOCK_HZ
- the timer header to use
- the interrupt controller header to use
This changes the comments regarding the size of the TCB to be more
generally accurate to help manually determine the size of the TCB for
different configurations.
This commit updates the aarch64 build to pass the c-parser.
- replace 0b constants with decimal
- remove empty array definition
- replace __uint128_t with uint64_t, and double the array size
- remove variable shadowing
No further verification guarantees are provided for aarch64 code.
This commit updates the ia32 build to pass the c-parser.
- replaces ++i with i++
- use void in functions with no parameters
- add a missing typecast
- remove a void cast of an unused variable
It does not provide any verification guarantees about ia32 code.
The SBI memory was mapped outside the kernel window. This would trigger
an instruction access fault on some hardware, when the bootloader has set
up PMP to protect the SBI memory. Instead of protecting a particular memory
region, the PMP locks the entire page table entry that covers the region.
The PADDR_LOAD and kernel base are adjusted to have the SBI memory
included in the kernel window. So that the SBI memory can be mapped as
part of the kernel image to a separate page table entry. This also
avoids the kernel to allocate untyped memory from the SBI region.
These files can be included normally using libsel4 include paths. This
removes situations where the same file is available under different
include paths due to symlinking into different directory structures.
Now these bitfield definitions are generated from the same source file
in the kernel and libsel4, and also result in the same include path: <sel4/shared_types_gen.h>
The previous 510GiB mapping was chosen to make it easier to eyeball addresses
while debugging: it was trivial to determine the physical address that a virtual
address pertained to in the kernel with this mapping.
This was no longer considered to be a necessary benefit, so this is being
changed.
The C parser produces abbreviations for local variables that depend on
the variable type and the order they appear in the source.
The signature for `get_avail_p_reg` on RISCV has a different type for
`i` than every other function, which causes issues when `hardware.h` is
included early in `kernel_all.c_pp`. Changing the type to `word_t`
avoids these issues.
-Use debuglist for runqueues and filter idle and root thread.
-Refactor sendEPQueue.
-Add multicore support.
-Added TCB_COMMAND, kernel now does translation
depending on how it's configured.
Clang doesn't provide support for __attribute__((optimize ...)). There
are alternatives to provide the same functionality but due to how rarely
the kernel is compiled without optimisations, this can be added on
demand.
This change alters RISC-V fault handling to pass all non-VM faults as
user exceptions. As we cannot guarantee what the hardware will send us
in the scause register, we must handle all possible values.
It also makes fault handling more consistent with other architectures in
c_traps.c.
GCC accepts MCR/MRC instructions to modify fpu control registers. Clang
does not. VMSR/VMRS are instructions that the ARM specification suggests
to use when accessing fpu control registers.
