universalisos/docs/hal_espressif_audit.md

ESP32 HAL (hal_espressif) Deep Audit — SoC Support Catalog

Source: /home/fabiorafaelcoutada/portugalfuturista/rtos_ref/hal_espressif/ Date: 2026-07-16 Purpose: Catalog ESP32 peripheral drivers and HAL code available for potential UOS microkernel integration Repo: Zephyr HAL module for Espressif SoCs (Apache-2.0)

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1. OVERVIEW

1.1 Repository Identity

• Name: hal_espressif — Zephyr HAL module wrapping ESP-IDF components
• Structure: components/ (synced ESP-IDF sources) + zephyr/ (Zephyr integration/adaptation layer)
• Sync source: ESP-IDF master, synced via tools/sync/hal-sync.sh, with Zephyr adaptation patches

1.2 Supported SoC Variants (14 total)

SoC	Architecture	CPU Cores	Series	Key Features
ESP32	Xtensa LX6	2	ESP32	Wi-Fi + BT + BLE, dual-core
ESP32-S2	Xtensa LX7	1	ESP32	Wi-Fi, USB OTG, single-core
ESP32-S3	Xtensa LX7	2	ESP32	Wi-Fi + BLE 5.0, AI acceleration, USB OTG
ESP32-C2	RISC-V	1	ESP32-C	Wi-Fi 4 + BLE 5.0, low-cost
ESP32-C3	RISC-V	1	ESP32-C	Wi-Fi 4 + BLE 5.0
ESP32-C5	RISC-V	1	ESP32-C	Wi-Fi 6 + BLE 5.0 + 802.15.4
ESP32-C6	RISC-V	1	ESP32-C	Wi-Fi 6 + BLE 5.3 + 802.15.4 + Thread/Zigbee
ESP32-C61	RISC-V	1	ESP32-C	Wi-Fi 6 + BLE 5.0 (derivative)
ESP32-H2	RISC-V	1	ESP32-H	BLE 5.3 + 802.15.4 + Thread/Zigbee (NO Wi-Fi)
ESP32-H21	RISC-V	1	ESP32-H	BLE + 802.15.4 (derivative)
ESP32-H4	RISC-V	1	ESP32-H	BLE + 802.15.4 + AES/SHA HW (derivative)
ESP32-P4	RISC-V	2	ESP32-P	NO wireless, dual-core high-perf, MIPI CSI/DSI
ESP32-S31	RISC-V	1	ESP32-S	Wi-Fi + BLE (S3 derivative/RISC-V)

UOS Priority: ESP32, S3, C3, C6, and P4 are the most feature-rich targets for a microkernel.

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2. ESP-IDF COMPONENT CATALOG (68 components in components/)

2.1 Core System Components

Component	Path	Purpose
hal	components/hal/	Hardware Abstraction Layer — central low-level register access macros (LL), HAL wrappers
soc	components/soc/	SoC definitions — register headers, peripheral base addresses, capability Kconfig, linker scripts, interrupt maps
esp_common	components/esp_common/	Shared ESP-IDF utility code
esp_system	components/esp_system/	System init, reset handling, linker scripts per SoC, task WDT
esp_hw_support	components/esp_hw_support/	Hardware support: sleep, power management, MSPI timing tuning, modem clock, ETM, debug probe, LDO, USB PHY
esp_rom	components/esp_rom/	ROM API headers and symbols — per-SoC ROM function declarations, linker scripts for ROM overlay
esp_timer	components/esp_timer/	High-resolution timer subsystem (TG0 LAC on ESP32, SYSTIMER on all others)
esp_pm	components/esp_pm/	Power management framework
esp_mm	components/esp_mm/	Memory management helpers
esp_app_format	components/esp_app_format/	ESP application image format definitions

2.2 CPU Architecture Support

Component	Path	Purpose
xtensa	components/xtensa/	Xtensa ISA support (ESP32, S2, S3): config headers, exception handling, TRAX trace
riscv	components/riscv/	RISC-V ISA support (all C/H/P series): interrupt handling, CLIC/PLIC, LD scripts

2.3 Peripherals — Communication Interfaces

Component	Path	Peripheral
esp_hal_uart	components/esp_hal_uart/	UART
esp_hal_i2c	components/esp_hal_i2c/	I²C
esp_hal_i2s	components/esp_hal_i2s/	I²S (audio)
esp_hal_i3c	components/esp_hal_i3c/	I3C (newer SoCs)
esp_hal_gpspi	components/esp_hal_gpspi/	General-Purpose SPI
esp_hal_mspi	components/esp_hal_mspi/	Memory SPI (flash/PSRAM controller)
esp_hal_sd	components/esp_hal_sd/	SD/MMC host controller
esp_hal_usb	components/esp_hal_usb/	USB OTG / USB Serial/JTAG
esp_hal_emac	components/esp_hal_emac/	Ethernet MAC (ESP32 built-in, others via SPI)
esp_hal_twai	components/esp_hal_twai/	TWAI (CAN bus)
ieee802154	components/ieee802154/	IEEE 802.15.4 (Thread/Zigbee) driver

2.4 Peripherals — Analog / Sensor

Component	Path	Peripheral
esp_adc	components/esp_adc/	ADC (SAR ADC)
esp_driver_dac	components/esp_driver_dac/	DAC
esp_hal_ana_cmpr	components/esp_hal_ana_cmpr/	Analog Comparator
esp_hal_ana_conv	components/esp_hal_ana_conv/	Analog Converter
esp_driver_touch_sens	components/esp_driver_touch_sens/	Touch Sensor
esp_hal_touch_sens	components/esp_hal_touch_sens/	Touch Sensor HAL
esp_driver_tsens	components/esp_driver_tsens/	Temperature Sensor
esp_hal_asrc	components/esp_hal_asrc/	Asynchronous Sample Rate Converter

2.5 Peripherals — Timers / Control

Component	Path	Peripheral
esp_hal_systimer	components/esp_hal_systimer/	System Timer (SYSTIMER — RISC-V SoCs)
esp_hal_timg	components/esp_hal_timg/	Timer Group (GPTIMER — general-purpose timers)
esp_hal_rtc_timer	components/esp_hal_rtc_timer/	RTC Timer (low-power timer)
esp_hal_wdt	components/esp_hal_wdt/	Watchdog Timers (MWDT, RTC WDT)
esp_hal_ledc	components/esp_hal_ledc/	LEDC (LED PWM Controller)
esp_hal_mcpwm	components/esp_hal_mcpwm/	MCPWM (Motor Control PWM)
esp_hal_pcnt	components/esp_hal_pcnt/	PCNT (Pulse Counter)
esp_hal_rmt	components/esp_hal_rmt/	RMT (Remote Control — IR + programmable waveform)

2.6 Peripherals — DMA / Data Path

Component	Path	Peripheral
esp_hal_dma	components/esp_hal_dma/	GDMA / AHB DMA controllers (RISC-V SoCs: esp32c3/c5/c6/p4)
esp_hal_cordic	components/esp_hal_cordic/	CORDIC coprocessor (trig functions)
esp_hal_ppa	components/esp_hal_ppa/	PPA (Pixel Processing Accelerator — P4)
esp_hal_jpeg	components/esp_hal_jpeg/	JPEG encoder/decoder (S3, P4)
esp_hal_parlio	components/esp_hal_parlio/	PARLIO (Parallel IO — camera/LCD interface)

2.7 Display / Camera

Component	Path	Peripheral
esp_hal_lcd	components/esp_hal_lcd/	LCD controller (MIPI DSI, RGB, I8080)
esp_hal_cam	components/esp_hal_cam/	Camera interface (DVP, MIPI CSI)

2.8 Clocks / Power / PMU

Component	Path	Purpose
esp_hal_clock	components/esp_hal_clock/	Clock tree management (PLL, XTAL, APB frequency)
esp_hal_pmu	components/esp_hal_pmu/	PMU (Power Management Unit — newer SoCs: C5/C6/H2/P4)
esp_hal_regi2c	components/esp_hal_regi2c/	Internal REGI2C (bias/calibration for analog blocks)

2.9 Security / Crypto

Component	Path	Purpose
mbedtls	components/mbedtls/	mbedTLS with ESP hardware acceleration (AES, SHA, RSA, ECC, ECDSA via DMA)
esp_hal_security	components/esp_hal_security/	Security HAL (DS, HMAC, XTS-AES, key manager)
efuse	components/efuse/	eFuse controller — per-SoC eFuse field definitions, burning, reading
esp_hal_gpio	components/esp_hal_gpio/	GPIO (also esp_driver_gpio)
esp_event	components/esp_event/	Event loop / event system

2.10 Wireless Stacks

Component	Path	Purpose
esp_wifi	components/esp_wifi/	Wi-Fi driver — per-SoC wifi lib wrappers, remote WiFi, regulatory
bt	components/bt/	Bluetooth — controller per-SoC, BLE audio, BLE ISO, NimBLE/Bluedroid porting layer, NPL
esp_phy	components/esp_phy/	PHY (RF) initialization and calibration
esp_coex	components/esp_coex/	Wi-Fi + Bluetooth coexistence management
wpa_supplicant	components/wpa_supplicant/	WPA supplicant (Wi-Fi security: EAP, WPA2/WPA3, PASN)

2.11 Storage / Memory

Component	Path	Purpose
spi_flash	components/spi_flash/	SPI Flash driver — per-SoC flash init, chip support, encryption, mmap
esp_psram	components/esp_psram/	PSRAM (external SPI RAM) support
heap	components/heap/	Multi-heap allocator — per-SoC memory maps, ROM patches
esp_hal_mspi	components/esp_hal_mspi/	MSPI timing tuning for flash/PSRAM

2.12 Boot / Bootloader

Component	Path	Purpose
bootloader	components/bootloader/	2nd-stage bootloader — per-SoC linker scripts, micro-ecc
bootloader_support	components/bootloader_support/	Bootloader utilities: flash init per-SoC, flash encryption, secure boot V1/V2

2.13 Low-Power Coprocessors

Component	Path	Purpose
ulp	components/ulp/	ULP coprocessors — FSM (ESP32/S2/S3), RISC-V ULP (S2/S3), LP-Core (C5/C6/P4)

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3. HAL LAYER ARCHITECTURE

3.1 Three-Tier HAL Model

┌─────────────────────────────────────────┐
│  Driver Layer (esp_driver_*, esp_hal_*) │  ← Platform-independent APIs
├─────────────────────────────────────────┤
│  HAL Layer   (hal/*.h)                  │  ← Thin wrappers around LL
├─────────────────────────────────────────┤
│  LL Layer    (hal/esp32*/include/hal/)  │  ← Per-SoC inline register access
├─────────────────────────────────────────┤
│  Register Layer (soc/esp32*/register/)  │  ← Generated register structs
└─────────────────────────────────────────┘

3.2 Shared HAL Headers (components/hal/include/hal/)

Header	Purpose
assist_debug_hal.h	Debug assist HAL
cache_hal.h / cache_types.h	Cache control HAL
color_hal.h / color_types.h	Color format conversion HAL
debug_probe_types.h	Debug probe types
efuse_hal.h	eFuse HAL
etm_hal.h / etm_periph.h / etm_types.h	Event Task Matrix
hal_utils.h	HAL utility macros
interrupt_clic_ll.h	RISC-V CLIC interrupt controller LL
interrupt_intc_ll.h	Xtensa INTC interrupt controller LL
interrupt_plic_ll.h	RISC-V PLIC interrupt controller LL
lp_core_types.h	Low-power core types
memprot_types.h	Memory protection types
mmu_hal.h / mmu_types.h	MMU HAL
modem_clock_hal.h / modem_clock_types.h	Modem clock HAL
psdet_types.h	Pad-scan debug types

3.3 Per-SoC LL Headers (Example: components/hal/esp32c6/include/hal/)

Header	Covers
cache_ll.h	Cache control
cpu_utility_ll.h	CPU utility (waiti, etc.)
crosscore_int_ll.h	Cross-core interrupts
efuse_hal.h / efuse_ll.h	eFuse access
etm_ll.h	Event Task Matrix
lp_aon_hal.h / lp_aon_ll.h	LP always-on domain
lp_clkrst_ll.h	LP clock/reset control
lp_core_ll.h	LP core control
mmu_ll.h	MMU low-level
modem_lpcon_ll.h	Modem LP control
modem_syscon_ll.h	Modem system control
rng_ll.h	Random number generator
sar_ctrl_ll.h	SAR ADC control
assist_debug_ll.h	Assist debug

Per-SoC LL variation: ESP32-P4 adds axi_icm_ll.h, debug_probe_ll.h, l2mem_ll.h, lp_mailbox_ll.h, lp_spi_ll.h, lp_sys_ll.h. ESP32-H4 adds aes_ll.h, sha_ll.h, modem_etm_ll.h.

3.4 HAL Platform Port (components/hal/platform_port/)

Zephyr adaptation layer for ESP-IDF HAL: assert.h, check.h, config.h, log.h, misc.h

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4. SOC DEFINITIONS (Register Layer)

4.1 Per-SoC Register Files (Example: ESP32-S3 → components/soc/esp32s3/register/soc/)

Total: ~75 register headers for ESP32-S3 covering:

Category	Headers
System	apb_ctrl_*, system_*, syscon_*, rtc_cntl_*, sensitive_*
Interrupts	interrupt_core0_*, interrupt_core1_*
GPIO	gpio_*, gpio_sd_*, io_mux_*, rtc_io_*
Timers	systimer_*, timer_group_*
Comm	i2c_*, i2s_*, spi_*, spi_mem_*, uart_*
ADC	apb_saradc_*
Motor	mcpwm_*, pcnt_*, rmt_*, ledc_*
LCD/Camera	lcd_cam_*
USB	usb_*, usb_serial_jtag_*, usb_wrap_*
SD/MMC	sdmmc_*
DMA	gdma_*
Memory	extmem_*, peri_backup_*
Security	efuse_*, world_controller_*
Debug	assist_debug_*
SDIO	hinf_*, host_*

4.2 SoC Include Files (Example: components/soc/esp32c6/include/soc/)

Defines per-SoC: interrupt maps, GPIO signal maps, pin definitions, clock tree, memory maps, capabilities, ETM sources, power domain retention, boot modes.

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5. ZEPHYR INTEGRATION LAYER (zephyr/)

5.1 Per-SoC Init & Build (zephyr/esp32*/src/)

Each SoC provides 4 mandatory files:

File	Purpose
soc_init.c	Early hardware init — ROM log suppression, bootloader clock config, WDT reset handling, MMU reset, RTC config, clock tree init
soc_flash_init.c	Flash initialization
soc_random.c	Hardware RNG entropy source
linker/*.ld	ROM alias linker scripts

Key initialization flow (from soc_init.c):

1. soc_hw_init() — Suppress ROM logs
2. check_wdt_reset() — Dump WDT reset info if applicable
3. reset_mmu() — Reset MMU + cache (if dual-core)
4. bootloader_clock_configure() — Switch to XTAL, configure RTC slow/fast clocks, set APB freq, init REGI2C
5. ana_reset_config() — Enable BOD, super WDT, clock glitch reset (S3)

5.2 Port Layer (zephyr/port/)

Directory	Contents
port/boot/	ESP image loader (MCUboot-compatible)
port/bootloader/	Bootloader flash operations
port/heap/	Zephyr heap adapter
port/include/boot/	Boot headers: bootloader_init_common.h, bootloader_wdt.h, esp_image_loader.h, esp_mcuboot_image.h, app_cpu_start.h
port/include/	ADC calibration, heap adapter, SPI common, host flash cache, WiFi event
port/pincfgs/	Pin configurations per SoC (YAML): esp32, s2, s3, c2, c3, c5, c6, h2, p4
port/stubs/	Stubs for Zephyr linking: bt_stubs.c, coex_stubs.c, esp_now_stubs.c, ieee802154_stubs.c, phy_stubs.c, wifi_compat_stubs.c, wifi_stubs.c

5.3 Common Layer (zephyr/common/)

File	Purpose
console_init.h	Console initialization
esp_blockdev.h	Block device abstraction
esp_critical_section.h	Critical section helpers
esp_log.h	ESP logging macros
esp_newlib.h	Newlib integration
flash_init.h	Flash init header
sdkconfig.h	SDK config header
soc_flash_init.h	SoC flash init header
soc_init.h	SoC init header
soc_random.h	SoC random header

5.4 Kconfig (zephyr/Kconfig)

Key config options:

• ESP_PLATFORM — enables ESP-IDF code paths
• SoC series selection (SOC_SERIES_ESP32, ESP32S2, etc.)
• XTAL frequency (26/32/40/48 MHz)
• Bootloader flash offset, CPU frequency
• IDF_TARGET_ARCH_RISCV / IDF_TARGET_ARCH_XTENSA
• ESP_TIMER_IMPL_TG0_LAC (ESP32) / ESP_TIMER_IMPL_SYSTIMER (all others)
• Wi-Fi task core selection, BT controller config
• Sleep/power config (GPIO workarounds, flash leakage, PSRAM retention)
• Chip ID mapping (IDF_FIRMWARE_CHIP_ID)

5.5 Scripts

Script	Purpose
scripts/pinctrl/esp_genpinctrl.py	Generate pin control tables from YAML
scripts/partitions/esp_genpartition.py	Generate partition tables

5.6 West (west/)

West extension commands for serial monitor and flash tools.

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6. BINARY BLOBS (zephyr/blobs/ — fetched via west blobs fetch hal_espressif)

6.1 Per-SoC Wi-Fi Libraries

SoC	Libraries
ESP32	libcore.a, libespnow.a, libnet80211.a, libpp.a
ESP32-C2	libcore.a, libespnow.a, libnet80211.a, libpp.a
ESP32-C3	libcore.a, libespnow.a, libmesh.a, libnet80211.a, libpp.a
ESP32-C5	libcore.a, libespnow.a, libmesh.a, libnet80211.a, libpp.a
ESP32-C6	libcore.a, libespnow.a, libmesh.a, libnet80211.a, libpp.a
ESP32-S2	libcore.a, libespnow.a, libnet80211.a, libpp.a
ESP32-S3	libcore.a, libespnow.a, libnet80211.a, libpp.a

6.2 Per-SoC PHY Libraries

SoC	Libraries
ESP32	libphy.a, librtc.a
ESP32-C2	libbtbb.a, libphy.a
ESP32-C3	libbtbb.a, libphy.a
ESP32-C5	libbtbb.a, libphy.a
ESP32-C6	libbtbb.a, libphy.a
ESP32-H2	libbtbb.a, libphy.a
ESP32-S2	libphy.a (no BTBB — no BT)
ESP32-S3	libbtbb.a, libphy.a

6.3 Per-SoC BT/BLE Libraries

SoC	Libraries
ESP32	libbtdm_app.a
ESP32-C2	libble_app.a
ESP32-C3	libbtdm_app.a
ESP32-C5	libble_app.a
ESP32-C6	libble_app.a
ESP32-H2	libble_app.a
ESP32-S3	libbtdm_app.a

6.4 Coexistence Libraries

All SoCs with both Wi-Fi and BT: libcoexist.a (ESP32, C2, C3, C5, C6, H2, S2, S3)

Impact for UOS: All Wi-Fi, BT, PHY stacks are binary blobs — cannot be recompiled. Microkernel must either:

• Use the blobs as-is in a driver VM / passthrough
• Implement a raw packet shim that calls blob functions
• Forward to a companion core running the full ESP-IDF stack

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7. BOOT CHAIN

ROM Bootloader → 2nd-stage bootloader (components/bootloader/) → 
  → bootloader_support (flash init, secure boot, encryption)
  → Zephyr kernel entry → soc_init.c (soc_hw_init, check_wdt_reset, reset_mmu, clock_configure)
  → flash_init → full kernel boot

Bootloader features:

• Per-SoC linker scripts in components/bootloader/subproject/main/ld/esp32*/
• micro-ecc for secure boot verification
• Image format: ESP image header + segments
• MCUboot support via zephyr/port/boot/esp_mcuboot_image.h

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8. FEATURE MATRIX (SELECTED SoCs)

Feature	ESP32	ESP32-S3	ESP32-C3	ESP32-C6	ESP32-P4	ESP32-H2
Architecture	Xtensa	Xtensa	RISC-V	RISC-V	RISC-V	RISC-V
Cores	2	2	1	1	2	1
Wi-Fi	✓ (4)	✓ (4)	✓ (4)	✓ (6)	✗	✗
BT/BLE	✓	✓ (5.0)	✓ (5.0)	✓ (5.3)	✗	✓ (5.3)
802.15.4	✗	✗	✗	✓	✗	✓
USB OTG	✗	✓	✗	✗	✓	✗
USB Serial/JTAG	✗	✓	✓	✓	✓	✓
Ethernet MAC	✓	✗	✗	✗	✓	✗
CAN (TWAI)	✓	✓	✓	✓	✓	✓
LCD/Camera	✗	✓	✗	✗	✓ (MIPI)	✗
GDMA	✗	✓	✓	✓	✓	✓
SYSTIMER	✗	✓	✓	✓	✓	✓
PMU	✗	✗	✗	✓	✓	✓
ETM	✗	✗	✗	✓	✓	✓
LP-Core	✗	✗	✗	✓	✓	✗
ADC	✓	✓	✓	✓	✓	✓
DAC	✓	✗	✗	✗	✗	✗
Touch Sensor	✓	✓	✗	✗	✗	✗
Temp Sensor	✓	✓	✓	✓	✓	✓
SD/MMC	✓	✓	✗	✗	✓	✗
PSRAM	✓	✓	✗	✗	✓	✗
AES/SHA/RSA HW	✓	✓	✓	✓	✓	✓
Secure Boot V2	✓	✓	✓	✓	✓	✓
Flash Encryption	✓	✓	✓	✓	✓	✓

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9. KEY FILES FOR UOS PORTING

9.1 Must-have for any ESP32 target

File	Reason
components/soc/<soc>/register/soc/reg_base.h	Peripheral base addresses
components/soc/<soc>/include/soc/soc_caps.h	SoC capability defines
components/soc/<soc>/include/soc/interrupts.h	IRQ numbers
components/soc/<soc>/ld/<soc>.peripherals.ld	Peripheral memory map
components/hal/<soc>/include/hal/*_ll.h	LL register access macros
components/hal/include/hal/*.h	Shared HAL interfaces
components/esp_rom/<soc>/include/<soc>/rom/*.h	ROM API declarations
zephyr/esp32*/src/soc_init.c	Reference init sequence
zephyr/port/include/boot/esp_image_loader.h	Image format
zephyr/Kconfig	Required config options

9.2 Per-Peripheral Driver Files

Each esp_hal_* component follows the pattern:

• Platform-independent HAL: components/esp_hal_<periph>/
• Per-SoC LL: components/hal/<soc>/include/hal/<periph>_ll.h
• Register definitions: components/soc/<soc>/register/soc/<periph>_reg.h, _struct.h
• Clock management: components/soc/<soc>/include/soc/clk_tree_defs.h
• GPIO mapping: components/soc/<soc>/include/soc/gpio_sig_map.h

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10. RECOMMENDATIONS FOR UOS MICROKERNEL INTEGRATION

10.1 Low-Hanging Fruit (No Blobs Required)

• Core peripherals: UART, GPIO, I2C, SPI, timers, WDT, RTC — all pure register-level drivers
• DMA (GDMA/AHB-DMA): for RISC-V SoCs
• eFuse: Read chip info, MAC address, security state
• RNG: Hardware random via rng_ll.h
• Boot: Image format parsing, early init sequence

10.2 Medium Effort

• ADC/DAC/Touch/Temp: Analog peripherals with calibration
• SD/MMC: SD host controller
• Ethernet: Built-in EMAC (ESP32) or SPI Ethernet
• LCD/Camera: MIPI DSI/CSI, parallel interfaces (S3, P4)
• USB: OTG stack (S2, S3, P4)

10.3 Hard / Blob-Encumbered

• Wi-Fi: Requires libcore.a + libnet80211.a + libpp.a + libphy.a blobs
• BT/BLE: Requires libbtdm_app.a / libble_app.a + libbtbb.a + controller blobs
• 802.15.4: Requires PHY blob + IEEE 802.15.4 driver from ESP-IDF
• Coexistence: libcoexist.a needed when both Wi-Fi and BT active

10.4 Isolation Strategy Options

1. Driver VM: Run ESP-IDF as a guest VM with device passthrough for wireless peripherals
2. Split-core: Run ESP-IDF on one core, UOS on the other (dual-core SoCs only)
3. Re-implement: Write native UOS drivers for non-blob peripherals, skip wireless
4. Hybrid: Native drivers for simple peripherals, proxy/blobs for wireless

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11. SUMMARY

Metric	Value
Total ESP-IDF components	68
Supported SoC variants	14
Per-SoC register headers (avg)	~50-100 per SoC
Per-SoC LL headers (avg)	~10-20 per SoC
Shared HAL headers	20
Wi-Fi blob libraries	29 across 7 SoCs
PHY blob libraries	16 across 9 SoCs
BT/BLE blob libraries	7 across 7 SoCs
Zephyr per-SoC init files	4 per SoC × 9 SoCs
Zephyr stubs	7
Zephyr pin configs (YAML)	9

This HAL provides complete register-level access to every ESP32 peripheral — the building blocks for a microkernel are all present. The main constraint is the wireless stack being closed-source blobs, requiring either a driver-VM approach or companion-core architecture for Wi-Fi/BT/BLE support.