Fábio Coutada
059f96c948
- HARD_REALTIME_EVALUATION.md: full HRT audit - MICROKERNEL_*.md: complete architecture targets and implementation plan - PIKEOS_3LAYER_REPLICATION_PLAN.md: 3-layer replication strategy - PIKEOS_POSIX_AUDIT.md: POSIX compliance audit - RTOS_AUDIT.md: RTOS comparison - XTENSA_AUDIT.md: Xtensa ISA audit - BIBLIOGRAPHY_SAFETY_CRITICAL_HYPERVISOR.md: references
238 lines
11 KiB
Markdown
238 lines
11 KiB
Markdown
# UniversalisOS Microkernel — Universal Architecture Vision
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**Date:** 2026-07-14
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**Status:** DRAFT — Awaiting deep RTOS audit results
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---
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## The Vision
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```
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┌─────────────────────────────────────────────────────────────────────┐
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│ UniversalisOS Microkernel │
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│ "Runs on everything, hosts everything" │
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├──────────────┬──────────────┬──────────────┬───────────────────────┤
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│ Cortex-M0 │ Cortex-M4 │ Cortex-A53 │ x86 (Pentium+) │
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│ (no MPU) │ (MPU) │ (MMU) │ (VT-x if available) │
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│ 4KB RAM │ 64KB RAM │ 512MB RAM │ 4GB+ RAM │
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├──────────────┴──────────────┴──────────────┴───────────────────────┤
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│ Agnostic API Shell │
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├──────────────┬──────────────┬──────────────┬───────────────────────┤
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│ FreeRTOS │ ThreadX │ Zephyr │ POSIX (PSE51) │
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│ personality │ personality │ personality │ personality │
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├──────────────┴──────────────┴──────────────┴───────────────────────┤
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│ uos_* Type System (universal) │
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│ uos_task_t, uos_sem_t, uos_mutex_t, uos_queue_t, uos_timer_t │
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└─────────────────────────────────────────────────────────────────────┘
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```
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## Design Principles
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### 1. Universal Hardware Support
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- **ARMv-M (Cortex-M0/M0+/M3/M4/M7/M23/M33/M55/M85)** — No MMU, optional MPU
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- **ARMv-A (Cortex-A5/A7/A8/A9/A53/A72/A76)** — Full MMU
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- **ARMv-R (Cortex-R4/R5/R7/R8)** — MPU only
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- **RISC-V (RV32/RV64, with/without H-extension)** — Sv39/Sv48 or PMP
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- **x86 (Pentium+ with/without VT-x)** — Protected mode, optional EPT
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- **Xtensa (ESP32/ESP32-S3)** — No MMU, windowed registers
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- **MIPS (PIC32)** — Simple MMU or no MMU
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- **AVR (megaAVR/AVR-DA)** — 8-bit, no MMU, no MPU
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### 2. Memory Model Tiers
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```
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Tier 0: No MMU, No MPU (Cortex-M0, AVR, basic RISC-V)
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→ Cooperative scheduling only
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→ No memory isolation between tasks
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→ Stack overflow detection via guard patterns
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→ Static memory allocation only
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Tier 1: MPU only (Cortex-M3/M4/M7/M23/M33, Cortex-R)
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→ Preemptive scheduling with MPU-based isolation
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→ Fixed memory regions (8-16 regions typical)
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→ Stack + data isolation per task
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→ No virtual memory, no demand paging
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Tier 2: Full MMU (Cortex-A, RISC-V Sv39+, x86 protected)
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→ Full type-1 hypervisor
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→ Partition isolation (page-table-based)
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→ Virtual memory, demand paging, COW
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→ Guest OS boot (Linux, RTOS, etc.)
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Tier 3: Hardware Virtualization (Cortex-A with VE, RISC-V H-ext, x86 VT-x)
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→ Full hardware-assisted virtualization
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→ Nested page tables (EPT/NPT/G-stage)
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→ Guest OS runs unmodified
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→ Device passthrough
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```
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### 3. Agnostic API Shell (Mbed OS Pattern)
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```
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The kernel exposes uos_* primitives. On top of that, personality
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shells provide familiar APIs:
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uos_task_create() ← universal task creation
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uos_sem_init() ← universal semaphore
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uos_mutex_lock() ← universal mutex
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uos_queue_send() ← universal message queue
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uos_timer_start() ← universal timer
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↓ Personality shells wrap these:
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xTaskCreate() ← FreeRTOS personality
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tx_thread_create() ← ThreadX personality
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k_thread_create() ← Zephyr personality
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pthread_create() ← POSIX personality
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osThreadNew() ← CMSIS-RTOS v2 personality
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```
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### 4. The Port Layer (inspired by ThreadX)
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Each architecture gets a port directory with exactly 4 files:
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```
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kernel/ports/armv7m/
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uos_port_context.S — Context save/restore (PendSV handler)
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uos_port_dispatch.S — First task dispatch
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uos_port_timer.S — SysTick/timer interrupt handler
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uos_port.h — Port-specific defines, inline asm
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```
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The port layer exports exactly 5 functions:
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```c
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void uos_port_init(void); // Hardware init (NVIC, MPU, etc.)
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void uos_port_start_first_task(void); // Jump to first task
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void uos_port_yield(void); // Trigger context switch (PendSV/SVC/ECALL)
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void uos_port_enter_critical(void); // Disable interrupts
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void uos_port_exit_critical(void); // Re-enable interrupts
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```
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### 5. Target Hardware Matrix
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| Vendor | Chip Family | Arch | Tier | Port Priority |
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|--------|-------------|------|------|--------------|
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| ST | STM32F0/G0 | Cortex-M0/M0+ | 0 | P0 |
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| ST | STM32F1/F4/F7 | Cortex-M3/M4/M7 | 1 | P0 |
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| ST | STM32H7 | Cortex-M7 (MPU) | 1 | P0 |
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| ST | STM32MP1 | Cortex-A7 + M4 | 2 | P1 |
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| Nordic | nRF52832/840 | Cortex-M4 | 1 | P0 |
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| Nordic | nRF5340 | Cortex-M33 (TrustZone) | 1 | P0 |
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| NXP | LPC55xx | Cortex-M33 (TrustZone) | 1 | P0 |
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| NXP | i.MX RT1060 | Cortex-M7 | 1 | P0 |
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| NXP | i.MX 8M | Cortex-A53 + M4 | 2 | P1 |
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| Microchip | SAM D21/L21 | Cortex-M0+/M23 | 0/1 | P1 |
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| Microchip | PIC32MZ | MIPS32 | 1 | P2 |
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| TI | CC2652 | Cortex-M4 | 1 | P1 |
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| TI | AM62x | Cortex-A53 | 2 | P1 |
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| Espressif | ESP32 | Xtensa LX6 | 1 | P1 |
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| Espressif | ESP32-S3 | Xtensa LX7 | 1 | P1 |
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| Espressif | ESP32-C3 | RISC-V RV32 | 0/1 | P1 |
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| SiFive | HiFive1 | RISC-V RV32 | 1 | P1 |
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| GigaDevice | GD32VF103 | RISC-V RV32 | 1 | P2 |
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| Intel | Pentium+ | x86 32-bit | 2 | P2 |
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| Intel | Atom/Core | x86_64 + VT-x | 3 | P0 (exists) |
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| QEMU | virt | All arches | All | P0 (test) |
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### 6. Agnostic API Design
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```c
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/*
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* UniversalisOS — Universal Kernel API
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* All types use uos_ prefix. All functions use uos_ prefix.
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* This is the ONE API that personality shells wrap.
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*/
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/* Task management */
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uos_task_t* uos_task_create(const uos_task_attr_t* attr, void (*entry)(void*), void* arg);
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uos_status_t uos_task_delete(uos_task_t* task);
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uos_status_t uos_task_yield(void);
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uos_status_t uos_task_suspend(uos_task_t* task);
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uos_status_t uos_task_resume(uos_task_t* task);
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uos_task_t* uos_task_self(void);
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uos_status_t uos_task_set_priority(uos_task_t* task, uos_prio_t prio);
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/* Scheduling */
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uos_status_t uos_sched_start(void); // Start the scheduler (never returns)
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uos_policy_t uos_sched_get_policy(void);
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/* Semaphores */
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uos_status_t uos_sem_init(uos_sem_t* sem, uos_count_t count);
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uos_status_t uos_sem_destroy(uos_sem_t* sem);
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uos_status_t uos_sem_wait(uos_sem_t* sem, uos_tick_t timeout);
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uos_status_t uos_sem_post(uos_sem_t* sem);
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/* Mutexes */
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uos_status_t uos_mutex_init(uos_mutex_t* mutex, const uos_mutex_attr_t* attr);
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uos_status_t uos_mutex_destroy(uos_mutex_t* mutex);
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uos_status_t uos_mutex_lock(uos_mutex_t* mutex, uos_tick_t timeout);
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uos_status_t uos_mutex_unlock(uos_mutex_t* mutex);
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/* Message queues */
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uos_queue_t* uos_queue_create(uos_size_t msg_size, uos_size_t max_msgs);
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uos_status_t uos_queue_send(uos_queue_t* queue, const void* msg, uos_tick_t timeout);
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uos_status_t uos_queue_receive(uos_queue_t* queue, void* msg, uos_tick_t timeout);
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/* Event flags */
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uos_status_t uos_event_init(uos_event_t* event);
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uos_status_t uos_event_set(uos_event_t* event, uos_flags_t flags);
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uos_status_t uos_event_wait(uos_event_t* event, uos_flags_t flags, uos_tick_t timeout);
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/* Timers */
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uos_timer_t* uos_timer_create(uos_tick_t period, void (*callback)(void*), void* arg, bool periodic);
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uos_status_t uos_timer_start(uos_timer_t* timer);
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uos_status_t uos_timer_stop(uos_timer_t* timer);
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/* Memory */
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void* uos_mem_alloc(uos_size_t size);
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void* uos_mem_aligned_alloc(uos_size_t align, uos_size_t size);
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void uos_mem_free(void* ptr);
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/* Time */
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uos_tick_t uos_tick_get(void);
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uos_status_t uos_tick_delay(uos_tick_t ticks);
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uos_status_t uos_tick_delay_until(uos_tick_t* last_wake, uos_tick_t increment);
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/* ISR-safe variants (from interrupt context) */
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uos_status_t uos_sem_post_from_isr(uos_sem_t* sem);
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uos_status_t uos_queue_send_from_isr(uos_queue_t* queue, const void* msg);
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uos_status_t uos_event_set_from_isr(uos_event_t* event, uos_flags_t flags);
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```
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### 7. Personality Shell Architecture
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```
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kernel/
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├── src/
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│ ├── core/ ← Universal kernel (uos_* API)
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│ │ ├── uos_task.c
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│ │ ├── uos_sched.c
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│ │ ├── uos_sem.c
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│ │ ├── uos_mutex.c
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│ │ ├── uos_queue.c
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│ │ ├── uos_event.c
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│ │ ├── uos_timer.c
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│ │ ├── uos_mem.c
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│ │ └── uos_tick.c
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│ ├── port/ ← Architecture ports (4 files each)
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│ │ ├── armv6m/ ← Cortex-M0/M0+ (no MPU, PendSV)
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│ │ ├── armv7m/ ← Cortex-M3/M4/M7 (MPU, PendSV)
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│ │ ├── armv7a/ ← Cortex-A (MMU, SVC/IRQ)
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│ │ ├── armv8m/ ← Cortex-M23/M33/M55 (TrustZone, PendSV)
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│ │ ├── armv8a/ ← Cortex-A53/A72 (MMU, HVC)
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│ │ ├── riscv32/ ← RV32IMC (PMP, ECALL)
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│ │ ├── riscv64/ ← RV64GC (Sv39, ECALL)
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│ │ ├── x86/ ← 32-bit protected mode (TSS, INT)
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│ │ ├── x86_64/ ← 64-bit long mode (VT-x if available)
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│ │ ├── xtensa/ ← ESP32 (windowed regs, level-1 int)
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│ │ └── mips32/ ← PIC32 (simple exception handling)
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│ ├── personality/ ← RTOS personality shells
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│ │ ├── freertos/ ← xTaskCreate → uos_task_create
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│ │ ├── threadx/ ← tx_thread_create → uos_task_create
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│ │ ├── zephyr/ ← k_thread_create → uos_task_create
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│ │ ├── posix/ ← pthread_create → uos_task_create
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│ │ ├── cmsis_rtos2/ ← osThreadNew → uos_task_create
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│ │ └── arduino/ ← xTaskCreate → uos_task_create
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│ └── platform/ ← Board-specific BSP
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│ ├── stm32f4/
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│ ├── nrf52/
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│ ├── esp32/
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│ ├── imxrt1060/
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│ └── ...
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```
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