Based on OpenWrt main branch (shallow clone).
Added:
- target/linux/ramips/dts/mt7621_tplink_archer-ax53-v1.dts
Device tree for Archer AX53 v1 (MT7621DAT, MT7975DN WiFi 6)
- target/linux/ramips/image/mt7621.mk
Image build recipe appended to existing MT7621 target
- target/linux/ramips/patches-6.6/
Kernel patch for MT7621DAT DRAM initialization
- package/pf-router/
Portugal Futurista router meta-package (pf-mesh, pf-crowdsec, pf-mqtt, pf-health, pf-ota)
WARNING: UNTESTED — GPIOs and flash layout need serial console validation.
Both boards only list their board compatible in the root node, so they
do not match the realtek MIPS machine and hang early during boot.
Fixes: 7cc31af7bd ("realtek: convert to generic machine initialization")
Signed-off-by: Carlo Szelinsky <github@szelinsky.de>
Link: https://github.com/openwrt/openwrt/pull/24615
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Move FIP handling to target now that we compile ATF. This is to have always
in sync new ATF and new U-Boot if one of the 2 is already compiled.
Also add HIDDEN ops to enable autoselection of the U-Boot for the required
target. This is needed to prevent user to deselect the U-Boot package
causing failure on ARTIFACTS generation.
Drop precompiled BL2 and BL31 as they can be now compiled from source.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24257
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add support for compiling Airoha ATF, based on a modified version of the
TF-A based on 2.10.
The package will clone the base TF-A and apply the modified source and
pre-compiled objects (DDR calibration, eFUSE handling, TX/RX path...) to
correctly compile.
An helper script is added to implement the same format used for special BL2
handling. BL2 is composed of 3 sub-phase with a initial BL21, a BL22 that
loads a LZMA decompressor and BL23 that actually calibrate and loads BL31
ATF.
Also a special flash_table is used to handle SPI-NAND externally to the
BL2, a special Host target is added for that.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24257
Signed-off-by: Robert Marko <robimarko@gmail.com>
The kernel config refresh done with commit
ada7ded disabled the Airoha PM Domain driver
due to the broken Kconfig dependency fixed with an earlier commit.
Add the missing symbol to enable the driver again. Also do a another
kernel config refresh to resolve some dependent PM domain symbols.
Fixes: ada7ded ("airoha: an7583: refresh kernel config")
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The clk-en7523 driver tries to look up the chip-scu regmap via the
"airoha,chip-scu" phandle first. If absent, it falls back to a
compatible-based lookup with syscon_regmap_lookup_by_compatible().
The AN7583 DTSI already had the phandle but AN7581 did not, relying
on the fallback instead. Add it so the DT explicitly describes the
connection and both platforms use the same lookup path.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
dev_pm_domain_attach_list() returns the number of attached PM domains
on success (a positive count), or a negative error code on failure.
The airoha-cpufreq driver checks 'if (ret)' which treats a successful
attachment as an error.
Fix by checking 'if (ret < 0)' like all other users of this API.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add SoC compatible for AN7583 to PM domain driver (the cpufreq driver
already has it).
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The AIROHA_CPU_PM_DOMAIN option was added inside the MediaTek PM Domains
menu, which depends on ARCH_MEDIATEK || COMPILE_TEST. Since Airoha
platforms use ARCH_AIROHA, the menu is invisible during kernel
configuration, silently dropping AIROHA_CPU_PM_DOMAIN. This breaks
running `make kernel_menuconfig`.
Add ARCH_AIROHA to the menu dependency so that this option and its
dependencies (PM_GENERIC_DOMAINS, PM_GENERIC_DOMAINS_OF) remain
enabled on Airoha targets.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The prom initialization is a bit of a mess now with all these
model and soc family checks. And realtek_read_model() function
is the worst offender of all as it goes through all of the model
info register from different SoCs just to read details from one
of them.
We can make use of the .data property in realtek_of_match to
clean things up so that each soc family has its own way of
initialization and reading model details.
Create a struct that will be used for that and add all of the
soc data structs for all chip families.
With all that, remove realtek_read_model() function and most
of the soc_info.family checks in various functions.
In addition, add the rtl960x compatibles along as well so that
rtl960x model info details has somewhere to be used. RTL8198D
is also added as it is part of RTL9607C family.
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/24588
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Some rtl9302 based boards use the realtek,rtl838x-soc compatible
in their device tree instead of the correct realtek,rtl9302-soc.
This is also the case for main rtl931x and rtl930x device tree files.
In preperation for utilizing device data in the board-realtek, fix
this up now so that these boards don't end up breaking due to incorrect
prom initialization caused by rtl838x-soc compatible.
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/24588
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Instead of putting in the target config where each refresh drops it,
lets disable it in the generic config.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Recent upstream cleanups moved switch port labels to the board level and
disabled switch ports/PHYs by default on the AN7583 SoC dtsi. This broke
ethernet on the Nokia XG-040G-MF since its board DTS was not updated to
explicitly configure and enable them.
Fix this by explicitly enabling gsw_port2-4 along with their respective
PHYs and restoring the "lan2", "lan3", and "lan4" port labels.
Fixes: ce55cdde26 ("airoha: an7583: move the switch port label from soc-level to board-level")
Fixes: d2698d325b ("airoha: an7583: disable all switch ports and PHYs by default")
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24606
Signed-off-by: Robert Marko <robimarko@gmail.com>
Disable write-protection on sdhci0, similar to the upstream
U-boot DTS. This also enables (obviously) the working overlayfs.
Link: https://github.com/openwrt/openwrt/issues/24602
Fixes: e050bb7946 ("zynq: add Bitmain Antminer S9 control board support")
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
The SCU IOMUX reset puts AN7583 pins 45-47 into GPIO mode. These pins
are shared with eMMC, but the generic eMMC function group only enables
the eMMC mode bit and leaves the GPIO overrides active, preventing the
card from initializing.
Add an AN7583-specific eMMC function group that also clears the GPIO
mode bits for the shared pins.
Fixes: d0110a25ed ("airoha: add pinctrl fixes for AN7581 and AN7583")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
There is no reason to add a custom kmod which is not even an7581
specific as its just the regular Mediatek MT7621 I2C driver.
So, simply enable the driver in kernel configs, drop the inclusion
per-board and remove the kmod definition.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The Kconfig symbol backing the HiFiBerry Studio driver was renamed
from SND_BCM2708_SOC_HIFIBERRY_STUDIO_DAC8X to
SND_BCM2708_SOC_HIFIBERRY_STUDIO. Update to the new symbol name.
Also add the new CONFIG_TOUCHSCREEN_ST7123 symbol, disabled by
default, to the generic config.
Signed-off-by: Joshua Covington <joshuacov@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24275
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
The quilt rebase of
0299-mmc-sdhci-of-dwcmshc-define-sdio-timeout-clocks.patch matched
the wrong occurrence of the two clk_disable_unprepare() calls for
pltfm_host->clk and priv->bus_clk, which appear both in
dwcmshc_probe()'s error path and in dwcmshc_remove(). This added a
clk_disable_unprepare(pltfm_host->timeout_clk) call inside
dwcmshc_remove() that is present in neither mainline Linux nor
raspberrypi/linux's rpi-6.18.y.
Drop it for now rather than carry an unverified addition. If it
turns out timeout_clk does need disabling on remove, it can be
reinstated with a clear rationale.
Fixes: 7105bec48f ("kernel: bump 6.18 to 6.18.40")
See: https://github.com/openwrt/openwrt/pull/24419
Signed-off-by: Joshua Covington <joshuacov@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24275
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
These patches were generated from:
https://github.com/raspberrypi/linux/commits/rpi-6.18.y
Patches were generated from the diff between linux kernel branch linux-6.18.y
and rpi-6.18.y from raspberry pi kernel source:
git format-patch -N linux-6.18.y..rpi-6.18.y (HEAD)
(HEAD -> 825dba6c63eeb40a62699d1f8a4aa3f02b0eaf49) as of 20260802
"Commit: pinctrl: bcm2835: Enable strict pinmux mode"
Exceptions:
- github workflow patches
- applied and reverted patches
- README patches
- (def)configs
- patches merged upstream
Patches refreshed against current OpenWrt-kernel.
Signed-off-by: Joshua Covington <joshuacov@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24275
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
SFP nodes are board-specific and do not belong in the SoC-level DTSI.
Remove them entirely since the AN7583 EVB boards do not reference them.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24264
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the standard 'led' node name for GPIO LEDs as required by the
devicetree specification.
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
[ adapted from commit f5bf8c2b94 ("airoha: correct led nodename") ]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24264
Signed-off-by: Robert Marko <robimarko@gmail.com>
Different boards use different port maps. Defining the port labels in
board-level is better.
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
[ adapted from commit e2f7ad08c7 ("airoha: move the switch port label from soc-level to ...-") ]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24264
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some boards only use some of them, so enable as necessary in the
board-level DTS.
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
[ adapted from commit 007aa5a51c ("airoha: disable all switch port and phy by default") ]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24264
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit adds support for Teralink TL3020 256mb wireless router.
Specification
-------------
- SoC : MediaTek MT7981B dual-core ARM Cortex-A53
- RAM : DDR3 256 MiB (ESMT M15T2G16128A, DDR3-1866)
- Flash : SPI-NAND 256 MiB (Winbond W25M02GV)
- WLAN : MediaTek MT7976 2.4/5 GHz Wi-Fi 6
- Ethernet : MediaTek MT7531 switch, 1x WAN + 3x LAN 10/100/1000 Mbps
(2.5GbE uplink via gmac0)
- USB : 1x USB 2.0 Type-A (power enable on GPIO 14)
- Buttons : WPS, Reset
- LEDs : 7x blue, 1x red
- UART : 4-pin header on PCB
- assignment : 3.3V, GND, TX, RX
- settings : 115200n8
- Power : 12 VDC, 1.5 A (barrel jack)
MAC addresses
-------------
EEPROM MAC is same for all the devices, but there is a `config2` partition
with unique MAC addresses:
| Interface | MAC source |
|-----------|--------------------------------------------|
| LAN | config2, offset 0x707 (ASCII, "lanmac") |
| WAN | config2, offset 0x787 (ASCII, "wanmac") |
| WLAN 2.4G | config2, offset 0x68a (ASCII, "wifi2gmac") |
| WLAN 5G | config2, offset 0x60a (ASCII, "wifi5gmac") |
The LAN MAC (gmac0) is the one printed on the device label.
Installation
------------
Factory bootloader is locked to 64mb partition layout, so OpenWrt U-Boot
has to be flashed first. Steps 1, 2 and 4 are run from a shell on the
stock firmware, where the 'bl2' and 'fip' partitions are writable - in
OpenWrt they are read-only, so the procedure cannot be repeated from
OpenWrt. Back up both partitions before overwriting them:
mtd read bl2 /tmp/bl2.bin
mtd read fip /tmp/fip.bin
1. Upload OpenWrt 'bl31-uboot.fip' and 'preloader.bin' images to the /tmp
dir of the router using scp protocol
2. Write fip and bl2 (replace bootloader):
mtd write /tmp/openwrt-mediatek-filogic-teralink_tl3020-256mb-bl31-uboot.fip fip
mtd write /tmp/openwrt-mediatek-filogic-teralink_tl3020-256mb-preloader.bin bl2
3. Place OpenWrt
'openwrt-mediatek-filogic-teralink_tl3020-256mb-initramfs-recovery.itb'
image on the tftp server (IP: 192.168.1.254)
4. Erase 'ubi' partition and reboot the router:
mtd erase ubi
reboot
5. U-Boot automatically boots the OpenWrt recovery image from the tftp
server to the RAM
6. Upload OpenWrt
'openwrt-mediatek-filogic-teralink_tl3020-256mb-squashfs-sysupgrade.itb'
image to the /tmp dir of the router (IP: 192.168.1.1) using scp
protocol
7. Connect to the router using ssh and run:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
sysupgrade -n openwrt-mediatek-filogic-teralink_tl3020-256mb-squashfs-sysupgrade.itb
Recovery
--------
1. Place OpenWrt
'openwrt-mediatek-filogic-teralink_tl3020-256mb-initramfs-recovery.itb'
image on the tftp server (IP: 192.168.1.254)
2. Press "Reset" button and power on the router. After ~10 sec release
the button.
3. Use OpenWrt initramfs system for recovery
Reverting to stock firmware requires writing the 'bl2' and 'fip' backups
taken above back with 'mtd write', then flashing the stock image; without
those backups there is no way back, because the stock bootloader cannot
be downloaded from the vendor.
Signed-off-by: Fil Dunsky <filipp.dunsky@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24518
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Wrap all swconfig-specific code in mt7530.c with #if IS_ENABLED(CONFIG_SWCONFIG),
including struct switch_dev, the vlan/port mapping tables and all
switch_dev_ops callbacks. Register access helpers (mt7530_r32/w32), the
PSC/HWTRAP definitions, and the small set of swconfig-only register
macros and MIB tables further up the file remain unconditional - the
latter two are unused-but-harmless when swconfig is disabled and are
left alone to keep the diff focused.
When swconfig is not compiled in, the driver performs only minimal
hardware init (disables MAC learning on all ports, applies the HWTRAP
fixup) and skips switch registration, mirroring the existing behaviour
of the "mediatek,no-swconfig" device tree property. This removes the
need for that property when building DSA-only images. The property is
still honoured whenever CONFIG_SWCONFIG is enabled (built-in or as a module).
A distinct log message is used for the compile-time case, to
distinguish it from the runtime "mediatek,no-swconfig" case in dmesg.
Also switch the existing runtime "swconfig disabled" message from
pr_info() to dev_info(), changing its dmesg prefix from "mt7620: " /
"mt7530: " to the device's own prefix.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/24574
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Use the proper drivers for each device.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24076
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Done with make kernel_oldconfig
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24076
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Remove the 6.12 kernel configuration and patch stack after switching to 6.18.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24076
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Move mpc85xx to the 6.18 kernel after testing it as the testing kernel.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24076
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
USXGMII carries the line rate to the MAC in a Clause 37 code word, so the
link needs in-band signalling. Without "managed" the port is PHY managed,
phylink disables in-band on the PHY, and with the PCS now honouring
neg_mode neither end runs autonegotiation, so nothing crosses the system
interface.
Every USXGMII port in this target was missing the property: ten ports
across eight boards, all of them an Aquantia PHY on copper, none of them
an SFP cage. ipq8074-rt-ax89x already carried "in-band-status" on its
SGMII lan8, which is why a file-level search made it look covered.
Only the two ports on ipq8072-301w have been tested on hardware. The
remaining eight are the same PHY family behind the same PCS, are broken
today for the same reason, and cannot regress from a state where they
pass no traffic, but they have not been confirmed on a board.
That test ran on the 6.18 testing kernel, where phylink switches the PHY
side on through phy_config_inband(). On 6.12 the PHY has no such op and
0760-net-phy-aquantia-enable-USXGMII-MAC-autoneg.patch forces the same
bit unconditionally, so the end state matches, but no board has confirmed
it there.
Tested-by: Rudy Andram <rmandrad@gmail.com>
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/24420
Signed-off-by: Robert Marko <robimarko@gmail.com>
qca_uniphy_pcs_get_state_usxgmii() took the link from the USXGMII code
word's link bit. An AQR113C behind this XPCS never asserts it:
autonegotiation completes, the code word tracks the copper rate as the
media renegotiates and reports full duplex, and the link bit stays clear
the whole time.
Once the port is marked as in-band managed that bit becomes the carrier
gate, so the port never gets carrier, link_up() never runs, the port MAC
is never enabled and the XPCS keeps its 10G reset default.
Take the link from the 10GBASE-R receiver instead, the way
qca_uniphy_pcs_get_state_10base_r() does. It answers the only question a
PCS can answer on its own, whether the system interface is up. The code
word stays the speed source: the Aquantia driver reports RATE_MATCH_NONE
for USXGMII, so phylink does not substitute the PHY's speed and this is
where the port's rate comes from. The link bit is kept as an_complete,
which is what it actually describes.
Confirmed on a QNAP QHora-301w, where 10g-1 now reaches carrier against a
1G link partner and configures an address.
Signed-off-by: Rudy Andram <rmandrad@gmail.com>
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/24420
Signed-off-by: Robert Marko <robimarko@gmail.com>
The USXGMII autoneg enable was keyed on the interface alone, so the XPCS
ran Clause 37 autonegotiation whenever the interface was USXGMII, no
matter what negotiation mode phylink had selected.
On an out-of-band link the PHY sends no code words, and the XPCS is left
waiting for them. The SerDes trains and the receiver reaches block lock,
but no traffic crosses the system interface in either direction, so the
port looks up while passing nothing.
Which side turns the PHY off depends on the kernel. From 6.16 the
Aquantia driver implements config_inband, and phylink calls it with
LINK_INBAND_DISABLE on a PHY managed link, which clears
MDIO_PHYXS_VEND_PROV2_USX_AN. On 6.12, the kernel this target builds by
default, that op does not exist and the PHY side is instead forced on
unconditionally by 0760-net-phy-aquantia-enable-USXGMII-MAC-autoneg.patch.
Key the write on neg_mode rather than dropping it, so a link that really
does negotiate in-band keeps working. Once the USXGMII ports are marked
in-band managed, this resolves to the value the driver already wrote, so
no in-tree board changes register state here today.
Diagnosed on the OpenWrt forum by rmandrad, who arrived at the same
condition independently and confirmed on a QNAP QHora-301w that enabling
autonegotiation on both the PHY and the XPCS makes the 10G ports pass
traffic.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/24420
Signed-off-by: Robert Marko <robimarko@gmail.com>
ipq8074-nbg7815 and ipq8072-mx8500 both place the AQR firmware cell at
offset 0x28 to skip the QCOM MBN header, but their node names still say
0, so the unit address disagrees with reg and dtc warns about it.
nbg7815 also calls the node aqr-fw where every other board calls it
firmware.
Only node names change. Both are referenced by label from the PHY's
nvmem-cells, not by path, and reg is untouched.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/24420
Signed-off-by: Robert Marko <robimarko@gmail.com>
The PPE driver registers its DSA switch, and with it attaches every user
port's PHY, before the root filesystem is mounted. A PHY driver that is
only available as a module therefore always loses the race:
phy_attach_direct() finds no matching driver, falls back to genphy_c45
and binds it with device_bind_driver(), and nothing rebinds the PHY when
the real driver shows up later.
On the boards with an Aquantia 10G PHY that leaves the AQR running under
the generic Clause 45 driver. It never loads its firmware, from the nvmem
cell or otherwise, and its system interface is never configured, so the
10G port does not pass traffic. Boards that provision the firmware from
flash have therefore never had that path execute at all.
The driver was built in until commit 8c3bcc198936 ("ipq807x: move AQR
driver from built-in to kmod"), which made it a module so that
IS_REACHABLE(CONFIG_HWMON) would evaluate true and the temperature
sensors in the AQR would be usable as thermal zones. That was correct at
the time: the ethernet driver then attached PHYs from userspace, so a
module was in place early enough, and hwmon was not built in.
Neither still holds. HWMON is compiled in on this target, so building the
PHY driver in keeps its hwmon support, and the PPE driver attaches PHYs
from its own probe. Build it in, as is already done for the AT803X and
QCA807X PHYs here.
CRC_ITU_T, which the driver selects for the firmware image
checksum, follows it from module to built-in.
Both symbols go in the ipq807x and ipq60xx config-default rather than
the target's per-kernel config. Every board with an AQR is on one of
those two subtargets and ipq50xx has none, and a subtarget's
config-default is merged for whichever kernel version the target
builds, so the 6.18 kernel picks them up as well.
kmod-phy-aquantia goes with it. The package builds empty once the symbol
is built in, because KernelPackage/install skips a module listed in
modules.builtin, but ModuleAutoLoad still runs and would ship
/etc/modules.d/18-phy-aquantia naming a module that no longer exists.
Drop it from the subtarget defaults and from the one ipq60xx device
that listed it, matching AT803X_PHY and QCA807X_PHY which carry no
kmod on this target.
Reported-by: Rye Sears <xlighting2017@users.noreply.github.com>
Tested-by: Rye Sears <xlighting2017@users.noreply.github.com>
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/24420
Signed-off-by: Robert Marko <robimarko@gmail.com>
The existing interrupt handling of the ethernet driver worked
well until the driver implemented receive fragment handling.
This change uncovered a constellation that did not exist before.
A received packet is written into the page pool with multiple
fragments. On RTL93xx the head-of-line (HOL) feature limits
the number of receivable fragments perfectly. There will never
be a "buffer full" situation where the hardware only encounters
ring buffers that are held by the Linux kernel. On RTL83xx
this is slightly different:
- The driver programs free floating rings
- Only the ownership flag of the ring buffer decides if the
hardware can hand over a packet to the CPU.
- So the hardware can receive a packet even if it does not
completely fit into the available fragments.
With this there is a small chance that
- The buffer has less space than a just received packet
- The hardware generates an overflow (RUN OUT) interrupt
- With no completely received packet the hardware DOES NOT
generate a receive (DONE) interrupt.
So it is not sufficient to just look on the DONE interrupts.
The RUN OUT interrupts must be inspected as well. As the
current logic is quite cryptic enhance this as follows:
- Provide new RTL83xx/RTL93xx specific helpers
- Add new callbacks to the driver configuration structure
- Link the configuration with the new helpers
- Use the callbacks where needed.
While we are here:
- Enable only interrupts for active receive rings. Until
now the driver activated all receive interrupts (8/32)
although it supports only 2 rings.
- Use DIV_ROUND_UP instead of classic division for register
calculation.
Link: https://github.com/openwrt/openwrt/pull/24538
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The zynq target now supports 6.18 kernel as testing.
Compile-tested: all boards
Runtime-tested: Antminer S9
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
