* Fix endianness issue by passing `cs_ppc_op.reg` instead of `.imm` to cs_reg_name.
The issue with using the `.imm` union member is that it is a `st64` while `.reg` is an enum (on SystemZ 32bit wide).
On little endian systems `.reg == .imm`. Not so on big endian systems. In which
case it is `.reg == .imm >> 32`.
* Set correct test for broken instruction `bne cr5, <target>`.
See issue: https://github.com/capstone-engine/capstone/issues/1914
* Print a warning if config for VM was NULL.
* Add warning if register is not added to VM due to overlap.
* Update PPC register profile.
* Add vector and float registers. As well as some control and system registers.
* Enable to write values 4bit registers.
* PPC: Uplift most common instructions.
* Print warning if reserved SPR instruction is encountered.
* Update PC/LR addresses and add ca32 writes.
* Write cache needs to get flushed so load and store tests don't share the same memory.
* Add missing T/F branch mnemonics.
* Add Move to/from CR/CR0-7
* Fix TA address calculation for branch instructions.
* Add branch tests for branch mnemonics.
* Add XNOP
* NOP cache touch instructions.
* Add undocumented ATTN instruction to the not_implemented group.
* Add isel instruction.
* Implement CRCLR, CRSET, CROR.
* Add CNTLZ instructions.
* Add mcrf instructions.
* Add inacive test for cmpb.
* Add Load bytes reverse instructions.
* Add test and add address alignment to dcbz.
* Add eqv test
* Correct DIV and MUL operations
* Add div tests.
* Add tests and correct MT/MFXER
* Remove register ca32, ov32
* Remove explici setting of cr register because QEMU does not do it. Otherwise we get a mismatch in the trace
* Simplify carry set for add and sub. Sub instructions are exclusivly defined with addition. Hence no sub case needed.
* Unify BD and fix branch instructions. Fix: Check the single bit not the cr reg
* Document Conditional branches and replace NOPs with EMPTY
* Add mulli instruction to double word instructions.
* Fix ca set for shift instructions:
* ca value had to be determined before the shift happened. The wrong ca value was calculated if the src and target reg were the same.
* Replace NOP wit EMPTY.
* Use MSB isntead of SLT.
* Brought fixup of ADD and SUB instructions: The add and sub instructions had several issues which let to incorrect execution.
* The carry was incorrectly if three add operations happened (only the last add were checked, not both).
* The carry was incorrectly set if the src and target register matched.
* Same applies for the CR bit.
* It was too complex. Several local variables were introduced for this.
* Set result in local var, since it would change if src and target reg are the same.
* Remove MTMSR and MFMSR since it is too complex and untestable currently.
* Use unsigned int for shift. Otherwise the 0x1c shift produces a runtime error since 0xf is int as default.
* Fix mtxer: Only write flag bits.
* Let NOT_IMPLEMENTED macro return NULL.
* Mark st[wd]cx and l[wd]cx as not implemented.
* Increase dcache_line_size to 128 bytes.
* Fix cntlz for ppc32. m was set incorrectly, since it is 0 not 32 for 32bit cpus.
* Fix isel: Use op.crx reg instead of imm.
* Unify helper function names: Prependnig `ppc_` mark as IPI
* Add more "Move to SPR" cases.
* MULLI opeartes only on double word on 64bit CPUs.
* Most registers are now assigned the control register type and no longer show up in the ar command.
* Fix xor if dest and src registers match by saving result in local var.
* Fix BE/LE issue for Load BRX instructions.
* Fix shifts: Use only lower 6bits of n.
* User Pure local variables for ROT macros.
* Fix rldimi instructions.
* n was not inverted.
* more than 6 bits of n could be used
* Add 32bit emulateme tests.
* Add 64bit emulateme tests.
* Determine lg(v) in inline function.
* Calculate CR bit in C not in the VM.
* Check if `~mask = 0` and skip mask calculation if yes.
* Check for `sh == 0` and skip rotations where possible.
* Remove `la` instruction. `la` is a mnemonic for `addi`.
* Remove SPR instructions which are not supported by QEMU or not traced yet. For most set/read SPR instructions QEMU segfaults.
In case of SPR 1 (xer), 8 (lr) and 9 (ctr) the assembler resolves them to their mnemonics (mtxer, mtlr etc.). This means the code here is never reached.
To test the get_xer code MFXER was added again. The rz-tracetests will fail for this instructions (due to missing ca32, ov32). But this case is covert in an issue.
* Chane HexInsn -> HexInsnContainer in asm plugin.
* Make HexInsn -> HexInsnContainer in hexagon_disas.c
* Add function to set concatinate textual disassembly parts.
* Switch expressions, fix segfault.
* Print number of unhandle ops, if they can not be added to RzAnalysisOp.
* Add lookup function to determine sub-instructions for duplex iclass.
* Fix asm tests.
* Add memcpy for instruction containers
* Fix off by one.
* Fix segfault if the packet held only the instruction which is currently resolved. `hic->bin.insn` would be NULL in this case.
* Remove duplicate index name.
* Set instruction address.
* Clean up hic->parse_bits use
* Fix: .new registers were not resolved dur to too early return.
* Fix rebase mistakes.
* Add missing code
* Fix build error: Use sizeof(`text_infix`) since it is way smaller than `text`
* Initialize `HexInsn` inside `setup_new_hic`. Fixes NULL access.
* Mark RzAsm/RzAnalysis members as deprecated and fix typo.
Although the reg profile was not really used yet it will be relevant for the RZIL uplifting.
Introduces:
* Double/quadruple registers now properly overlap with their counterparts.
* Registers have correct types assigned (vec, ctr, sys etc. Before, all regs were of type gbr)
* Consistent register names (asm name style: c3:2, r31 etc, alias style: lc1:sa1, lr etc.)
* Adds _tmp registers in the profile. Later used by uplifted instructions (think of .new registers).
* Add function to add config node to config by `RzConfigNode*`
* Move `SET<NODE>` macros to `rz_config.h`
* Add un/set functions for plugin specific configs.
* Add RzConfig and node setter to hexagon plugin.
* Use plugins RzConfig to determine sdk syntax setting.
* Use plugins RzConfig to determine if numbers should be signed.
* Use plugins RzConfig to determine if immediate hash should be printed.
* Remove unused parameter `rz_asm`.
* Remove unused variable.
* Remove unused callback.
* Remove unused flags from `RzAsm`
* Fix asm tests: Add NULL check; Set correct sign in asm test.
Leaks detected by running rz-test with asan-built rz-asm. The sbc
instructions didn't do the carry subtraction right and threw away half
of the computation, which is why it was detected through leaks.
* Add option to print instruction packets syntax in objdump style.
* Add the config `plugins.hexagon.sdk` to toggle syntax.
* Remove unused trimming.
* Trim only newlines from the assembly string.
* Add new trim functions to allow trimming of certain chars.
This adds RzIL lifting for all legal 6502 ops, except the special bcd
modes of adc and sbc for now. The lifting of every one of these ops is
covered by an asm test, making sure all IL is valid. Some manual
execution tests are available too, including one that runs a simple
real-world xor-"decryption" loop.
The lifting has not been tested against traces yet, so minor mistakes in
the semantics are currently expected.
Also new in this commit:
- Uses system registers as defined in LLVM definitions.
- Several new Hexagon v69 (HVX) instructions.
- File header now has the LLVM commit and timestamps of the source file generation.
Before:
store(key:var(v:ptr), value:add(x:load(key:var(v:ptr), mem:0),
y:int(value:1, length:8)), mem:0)
After:
(store 0 (var ptr) (+ (load 0 (var ptr)) (bv 8 0x1)))
S-Expressions like this are more concise and will be trivial to parse,
in case we want a parser for this later. It is also very similar to what
BAP uses, so it will be easier to compare.
* Add support for: v5-v68+HVX, System instructions/register; Change plugin design to monolithic; Basic ELF-reloc patching.
- Update instruction set to v5-v67 + HVX.
- Introduce monolithic plugin architecture to reverse opcodes in the same functions.
- Analysis and Asm functionality was previously seperated and let to inconsistensies and incorrectly reversed opcodes.
- Add missing system instructions and registers.
- Enable search for immediates.
- Mark packets of instructions.
- Set more analysis data in RzAnalysisOp.
- Add basic ELF-reloc patching.
- Fix several disassembly and analysis bugs.
- Jumps were not aligned to packet begin.
- Endloop packets were not marked as such.
- Rs.New registers were incorrectly disassembled.
- Calling convention was out of date.
- Add several formatting configs for the produced disassembly.
- Dis/Enable UTF-8.
- Print or omit # prefix of immediates.
- Print signed immediates as signed or unsigned integers.
