The PGD constants refer to the top level mapping object used by the
kernel for its own private mappings. Userlevel cannot create any PGD
objects and so these constants don't belong in libsel4.
Configure the ability to trap on vcpu WFE/WFI calls. If enabled,
user-level would need to schedule a future interrupt when a given
vcpu invokes a WFE/WFI instruction. This otherwise leaving the
vcpu in a disabled state. An application can choose to
disable the trap if it doesn't want to handle the instruction and
schedule a future interrupt.
Cache flush operations are applied through the kernel window mapping in
hyp mode. This requires an extra check that the frame being provided is
accessible through the kernel window.
Added support for reading and writing additional virtual timer
registers for vcpu hw read and write accesses. These include the
compare value register (CNTV_CVAL) and offset register (CNTV_OFF),
each represented as two 32 bit (high and low) registers on aarch32 and
as single 64 bit registers on aarch64.
Added support for explicitly saving and restoring the virtual
timer registers when the vcpu is enabled and disabled. This
ensures when the vcpu is switched in and out, the virtual timer
registers are restored to a state that is consistent to when
it was last run.
By default the CNTVOFF register will be updated by the kernel to
accumulate the time the VCPU is not running. From the guest this will
result in the VCNT register not increasing when the VCPU is suspended.
This behavior can be turned off by disabling the
KernelArmVtimerUpdateVOffset config option.
This commit introduces a new fault type, seL4_Fault_VPPIEvent.
This change means the kernel can reserve PPI interrupts and virtualise
them via delivering the irq to the active vcpu through a
specific fault. This enables multiplexing PPI IRQs across multiple VCPUS
which requires correctly masking and unmasking the IRQ depending on
which VCPU is running.
A new VCPU invocation, seL4_ARM_VCPU_AckVPPI is also added for
acknowledging the handling of the IRQ. This takes an IRQ as a parameter
but will only accept IRQ numbers that are sent as VPPIEvent faults.
Co-authored-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
Added constant defintion for the "cntpct_el0" and " cntv_ctl_el0"
register. This being consistent with the 32bit mode definition
of the same registers.
Move vcpu functions that are specific to a particular Arm architecture
version into the relevant header files. Also move some generic functions
into the generic vcpu header file for use by arch specific headers.
Specifying a function name prefixed with 'm' is not compatible with
clang.
For 32 bit, call vmlaunch_failed explicitly from within the assembly.
Requires adding the USED attribute to vmlaunch_failed as it is only
referenced in a string literal.
For 64 bit, move the address of vmlaunch_failed into rax as an integer
rather than loading it as the address of a function (lea).
This inline function doesn't get inlined with -O3.
It affects the cold cache performance, so use always_inline
attribute to tell compiler always get it inlined.
Depending on the platform, IPI has a slightly different interface.
Explicitly cast from the more speific enum type to the generic
and vice versa when calling in and out of generic code.
Another possibility would be to typedef a specific enum on RISCV
platforms that aliases the one currently used. Then casting would only
have to take place when passing args to function calls.
In circumstances where values are negative and
compared to unsigned variables, clang will
error saying that this is always true. Include
early break conditions that check for this
Setting `-target` flag explicitly is unnecessary. Whenever this needs to
be explicitly passed through, the coompiler id should be checked.
Changes to the musl build system makes the explicit `C_COMPILER`
variable useless.
For some reason the kernel documented and maintained constants for a
512MiB 'huge page' in riscv32 which is not part of the specification.
The references and constants are removed
Explicitly create a struct definition for irq_t on SMP Arm
configurations. This makes it a lot harder to mistakenly use the wrong
irq encoding when moving an irq between a cnode index and hardware irq
number / core. A couple areas where this was being handled incorrectly
was fixed as part of the refactor. When performing an ipi for masking
PPI interrupts, the idx encoding is used as it fits into a single word.
Every platform has to implement a standard set of interrupt interfaces
that the kernel uses to interract with a machine's interrupt controller.
Providing a single header file for each of these functions provides a
single location to document their behavior.
Both the private and global arm timers are clocked from the same source
and neither of the drivers apply a pre-scaler so the frequency should be
the same in both configurations.
The frequency of this clock is based on PLL1 which could potentially lie
anywhere in the range of 650MHz to 1.3GHz. The value determined for MCS
appears to correctly agree with the user-level timer which appears to be
correctly implemented.
The DTS in the 'tools' directory is missing information about the EPIT2
timer. We add the entry into the corresponding overlay DTS file so that
the EPIT2 node will be included into the resulting DTB.
The corrected user timer showed that the estimated value for the kernel
timer used in MCS was incorrect. It has been re-calculated on the fixed
user-level timer.
According to the implementation of the user-level timer the primary
clock source (`m_clock`) can only be configured to 12MHz on TX1 and TK1
(see the comment in `libplatsupport` at
util_libs/libplatsupport/src/mach/nvidia/timer.c:213).
This should allow the TX1 to pass all MCS tests.
Currently the vcpu_switch function is called in the setVMRoot function
after possible early returns. In order to make sure the vcpu is
always switched, the call is moved into Arch_switchToThread before the
call to setVMRoot.
...and other tweaks.
* Clarify the synonymy of Receive and Wait on non-MCS systems.
* Note that Receive takes a reply object on MCS systems, and not on
non-MCS systems. Also note redundancy of Wait on non-MCS systems.
* Use the full English word "Receive" when the discussion is at the
conceptual level. It still gets abbreviated in C context, where it also
receives the "seL4_" prefix.
* Try a little harder to explain what's the same and what's different
about a non-MCS "reply capability" and an MCS capability to a reply
object.
* Explain what MCS stands for at the beginning of the chapter. In the
manual's current organisation, this precedes by a few paragraphs the
term's first occurrence.
* Recast language about things being "on the MCS kernel" in favour of
describing "MCS" and "non-MCS" _configurations_ of the kernel. (We do
not refer to the "master" kernel in the manual--thankfully.)
* Correct doubled word "to to".
* Italicise "reply capability" to better distinguish it from the
(already italicised) "reply object".
* Add a TODO comment about hyphenation grief.
* Recast language of introduction to system calls.
* Rearrange system calls to present them in a more pedagogically useful
order.
* Add TODO comment for future manual organisation efforts.
This sets the first UART as the stdout-path dts setting in the
"chosen" node in the HiFive device tree.
Change-Id: Icb6b9abf999bdd8a278df5a2ba73ad492af06a24
