Split up the bit specific code into new folders and added 64-bit
support. Also, changed the device register sizes to be based off of
PAGE_BITS instead of a hardcoded number.
TIMER_CLOCK_HZ is set to the default clock rate from the ATF,
which is the same for both AARCH32 and AARCH64.It may require changes
to the FSBL to work correctly.
The Zynq UltraScale+ MPSoC (PLAT zynqmp) is a Multi-Processor SOC
made by Xilinx that has a quad-core Cortex-A53, a dual-core Cortex-R5
and an FPGA.
This adds 32-bit, single-core support on the the Cortex-A53 cluster.
This renames the previous irq_t enum into a platform_irq_t enum and provides irq_t
as a 'well defined' uint8_t typedef. Having irq_t be an integer type, and not an enum,
is necessary for consistency with verification. As part of explicitly defining irq_t
as an unsigned integer type the definition of irqInvalid is changed to prevent sign
extension leading to unexpected invalid comparisons.
Changes the name of paging structure entries to more clearly indicate the kind of object
they map to. Generally this is changing a `pde_small` to `pde_pt` to indicate that this
mapping refers to a page table, removing an inconsistency where `pde_large` indicated that
the mapping was for a large page. For the same reason the `ept_pde_4k` type is changed to
`ept_pde_pt` type to reflect what is present in the actual entry.
`pde_large` is left as 'large' and not explicitly given a size as code common between
ia32 and x86-64 manipulates these entities and 'large' is already a used abstraction
over the two potential page sizes so there is need to introduce a formal abstraction layer
and make the names in the structures more specific.
On the MCS kernel, Arch_migrateTCB is called in multiple places.
This commit moves the common code that is required when migrating a TCB
to a top level function to reduce boiler plate.
The VT-x implementation is not going to be verified at the moment, and so the code for
it needs to be hidden from verification, which we do by #ifdef'ing it out if the VT-x
is not enabled. As a result the VT-x configuration depends on a non verification target
The IOMMU implementation is not going to be verified at the moment, and so the code for
it needs to be hidden from verification, which we do by #ifdef'ing it out if the IOMMU
is not enabled. As a result the IOMMU configuration depends on a non verification target
Changing the register used for the IPC buffer is useful as the standard TLS model for
aarch64 is to use tpidr_el0 for the thread pointer, which we are presently using
for the IPC buffer. This therefore paves the way for implementing proper TLS support
on aarch64.
Since we are not using tpidr_el0 for the IPC buffer we need to save/restore (or at
least clear) this register on thread switch to prevent it being a user channel. Saving
and restoring of it is achieved by ensuring CONFIG_IPC_BUF_TPIDRURW is not set, which
as we are no longer using this strategy this will be the case. To that end as aarch64
only has one IPC buffer strategy this commit makes the choice of IPC buffer strategy
dependeont on aarch32.
This commit implements lazy FP save/restore mechanism, required for user threads
when they use the FPU. The following caveats take place:
* Only support synchronous exceptions. No support for asynchronous ones.
* VFP opcodes are used instead of normal instructions to discard compiler warnings/errors.
* Support is limited to specific ARM subarchitectures we support and tested this commit on.
* Disable the FPU by default if users are not using it to avoid channels.
* FPU support is not verified yet.
* Will not work properly if using a VM that's running besides other VMs/threads that are using the FPU.
Currently we assume CPU IDs to be linear and use HW CPU IDs as indices
to SMP-related arrays/state. This may change in the future (when
cluster-based SoC are supported).
cpuIndexToID converts a CPU index to a bit position in the case of ARM/GIC,
in order to send IPIs.
- don't print header every time
- drop address, it's not very useful and clutters the output
- add pretty header
- use new leading spaces feature in kprintf
When compiling the kernel as a whole program it is possible that these functions may
be inlined and not emitted in the resulting binary. However at the same time the
compiler may itself emit calls to these functions. Marking these functions as
externally visible tells the compiler that there may be more usages of them than
it sees immediately in the source code, in this cases usages that the compiler
itself is going to generate
In file included from ./kernel/src/api/faults.c:16:
In file included from ./kernel/include/api/syscall.h:19:
./kernel/include/api/debug.h:51:38: error: comparison of constant 'SysSend' (-3) with expression of type
'seL4_Word' (aka 'unsigned long') is always false [-Werror,-Wtautological-constant-out-of-range-compare]
if (ksKernelEntry.syscall_no == SysSend ||
~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~
./kernel/include/api/debug.h:52:42: error: comparison of constant 'SysNBSend' (-4) with expression of type
'seL4_Word' (aka 'unsigned long') is always false [-Werror,-Wtautological-constant-out-of-range-compare]
ksKernelEntry.syscall_no == SysNBSend ||
~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~
./kernel/include/api/debug.h:53:42: error: comparison of constant 'SysCall' (-1) with expression of type
'seL4_Word' (aka 'unsigned long') is always false [-Werror,-Wtautological-constant-out-of-range-compare]
ksKernelEntry.syscall_no == SysCall) {
~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~
- when CONFIG_DEBUG is enabled, track all threads
- when CONFIG_PRINTING is enabled, provide seL4_DebugDumpScheduler which
allows the user to dump the state of the kernel scheduler.
