Commit graph

4001 commits

Author SHA1 Message Date
Kent McLeod
c7d5bb0ed4 libsel4: Fix name for AARCH64_VSPACE_S2_START_L1
CONFIG_AARCH64_VSPACE_S2_START_L1 has the correct namespace for a kernel
config option.

Signed-off-by: Kent McLeod <kent@kry10.com>
2021-09-06 08:08:54 +10:00
Kent McLeod
b6de9db07a libsel4: Fix Config name for ENABLE_SMP_SUPPORT
CONFIG_ENABLE_SMP_SUPPORT has the correct namespace for a kernel config
option.

Signed-off-by: Kent McLeod <kent@kry10.com>
2021-09-06 08:08:54 +10:00
Kent McLeod
1d2a588bbf libsel4,config.h: Remove misleading #defines
autoconf.h is expected to contain all defined config options for an seL4
build configuration. Having these redefinitions were leftover from when
the verification build system didn't produce an autoconf.h file and set
the config separately.  Its more likely that these defaults would
incorrectly hide an include path misconfiguration and produce settings
that are inconsistent with the kernel's configuration.

Signed-off-by: Kent McLeod <kent@kry10.com>
2021-09-06 08:08:54 +10:00
Ben Leslie
5fb0a945bd Add 'x' bit to *verified.cmake
The verified.cmake files are designed to be executable scripts.
Ensure all have the 'x' bit.

Signed-off-by: Ben Leslie <benno@brkawy.com>
2021-09-03 14:39:28 +10:00
Alexander Fasching
560f215489
tools: Fix regex for ignore pattern (#535)
Signed-off-by: Alexander Fasching <fasching.a91@gmail.com>
2021-09-03 12:54:17 +10:00
Kent McLeod
e4262a90d2 arm,gic: GICv3 only supports max 16 list registers
Update GIC_VCPU_MAX_NUM_LR constant to reflect that only 16 list
registers are supported on GICv3. The kernel still reads the actual
number of supported list registers out of the GICH_VTR register so the
kernel would still do the right thing before this change.

Signed-off-by: Kent McLeod <kent@kry10.com>
2021-09-03 10:23:06 +10:00
Ben Leslie
0c6229d598 Add support for GICv3 virtualization
This adds sufficient kernel support for the GICv3 interrupt controller
to be used in a virtualization context on aarch64.

This set of changes has some limitations, however it is still an
improvement on the status quo.

Limitations:

1: This only provides support for aarch64. Anyone wanting support
for aarch32 + GICv3 + virtualization would need to add additional
code.

2: This code only supports 32 priority levels. Support for more
than 32 priority requires changing the get/set_gic_vcpu_ctrl_apr
interface. This is feasible, but requires a more invasive set of
changes. 32 priority levels has been shown to be sufficient in
practise.

Impacts on verification:

This set of changes should only impact Aarch64 Hypervisor
configurations. This is not yet verified so should not have
an impact on verification.

Level of testing:

This has been tested on an iMX8QXP based board. Testing
has at this point in time been limited to a single virtual
machine.

Note: support for this board is not yet upstrea, but is
currently being prepared.

Explanation of changes:

Ideally a new config item would not be required and this
could be driven purely by DTS and hardware.yml configuration.
However, the structures.bf requires changes. This can only
deal with config.h header files, not other more complex
header files. As such it was necessary to introduce a config
item which can be used for this purpose.

The appropriate platforms (as determined by examination of
DTS files) have been updated with the appropriate config
setting. This config setting only has any relevance if
hypervisor mode is already enabled, so should not cause
any difficulty for existing code or configuration.

Note: No testing has been performed on the updated
platforms.

There may be alternative factorings of this, which could
be considered in future work.

Signed-off-by: Ben Leslie <benno@brkawy.com>
2021-09-03 10:23:06 +10:00
Jimmy Brush
d653d9b2c6
Add missing error code in ARM IRQControlGetTrigger (#534)
Fixes #529

Signed-off-by: Jimmy Brush <code@jimmah.com>
2021-09-02 10:03:49 +10:00
Axel Heider
f46aac30b8 boot: remove ndks_boot.slot_pos_max
- The field 'slot_pos_max' from 'ndks_boot' is not needed, the value
  stored there is the constant BIT(CONFIG_ROOT_CNODE_SIZE_BITS).
- Improve the error message if the limit has been reached

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-09-02 08:44:24 +10:00
Gerwin Klein
a7b88f9378 x86 ioapic: make sure array is non-empty
CONFIG_MAX_NUM_IOAPIC can end up being 0 when the kernel is configured
as PIC-only. This code is then unreachable, but gcc-10 can't figure
that out and fails on array-out-of-bounds access (which would be
correct if the code were reachable).

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-09-01 16:34:26 +10:00
Gerwin Klein
2d0410b1ee vtx: fix EPT cache attribute setting
Credits for this one should go to clang-11, which correctly flags that
the big `||` always yielded true and was not doing what was intended.

This means, previously the only possible cache attribute for EPT was
EPTWriteBack.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-09-01 15:18:46 +10:00
Gerwin Klein
aec0f5a3f0 aarch64: make gcc-10 happy
The option -mno-outline-atomics used to be default before gcc-10 and
now needs to be provided explicitly. Without it gcc will produce
references to `__aarch64_ldadd8_acq_rel` which it expects to exist
in libgcc which we are not linking against.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-31 16:37:11 +10:00
Gerwin Klein
e3c2dbb26b docs: add link explaining license implications
Adding a link to Gernot's blog post that explains what GPL on seL4
means for other code. This is mainly intended for people who aren't
that familiar with what all of these licenses mean.

Closes #524

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-31 14:31:11 +10:00
Gerwin Klein
55cf30c8b1 trivial: use #ifdef instead of #if
`#if` fails if the symbol is not defined

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-31 11:59:17 +10:00
Axel Heider
a7194c1927 add comment about handleUnknownSyscall()
The function name handleUnknownSyscall() is slightly misleading, it
handles all non-standard seL4 syscalls used in debug builds also.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-31 10:53:31 +10:00
Axel Heider
f8c3ad0c58 add comment about empty Arch_finaliseInterrupt()
Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-31 10:53:31 +10:00
Axel Heider
7a4da705f0 boot/arm: clarify comment about cache flush
Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-31 10:53:31 +10:00
Axel Heider
54ae03f951 trivial: improve style for code and comments
Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-31 10:53:31 +10:00
Ben Leslie
e3eda12d03 Add support for the TQMa8XQP 1GiB module
TQ Group produces a system-on-module family called TQMa8Xx.

The user manual for this SoM is available here:

https://www.tq-group.com/filedownloads/files/products/embedded/manuals/arm/embedded-modul/TQ-Socket/TQMa8Xx/TQMa8Xx.UM.0104.pdf

This SoM comes in a number of different configurations.

The specific NXP SoC used, and the amount of memory are both
configurable.

The TQMa8XQP is the part number for the TQMa8Xx family configured with
the i.MX 8QuadXPlus SoC.

The datasheet for the SoC is available here:

https://www.nxp.com/docs/en/data-sheet/IMX8QXPAEC.pdf

In addition to the SoC being configurable the amount of SDRAM
on the SoM is also configurable.

The support provided in this PR is specifically for the TQMa8XQP
configured for 1GiB of memory. Note: Actual usable memory available
to the ARM application processor is 1022MiB.

System-on-modules rely on an appropriate carrier board.
Testing of this PR has been done on the MBa8Xx carrier board
that is available from TQ Group as part of their starter kit.

To the best of my knowledge there is nothing in this PR
that depends on the carrier board itself; all code is SoM
specific and should support any carrier board.

Note: This support is very specifically for the TQMa8XQP configured
with 1GiB of memory.

This may be a starting point for supporting other boards that
also have the NXP i.MX 8QuadXPlus SoC (as well as the i.MX 8DXP
and possibly other SoC in the i.MX 8 family).

Support is limited to the specific SoM due to the way in which
platform support currently works for seL4. Building a kernel
currently relies on the information from the DTS file (which is
SoM + RAM configuration specific). It would be preferable to
allow more generic support but SoC families but that is beyond
the scope of this PR.

Signed-off-by: Ben Leslie <benno@brkawy.com>
2021-08-31 08:38:25 +10:00
Chang Liu
65f94211cb x86: Mark idle_thread() as NORETURN
Mark the idle_thread() function as NORETURN for better static
analysis and compiler warnings.

Signed-off-by: Chang Liu <chang_liu3@brown.edu>
2021-08-30 10:46:12 +10:00
Chang Liu
604c7c106e x86: Always eliminate prologue for idle_thread()
The idle_thread() cannot perform any stack manipulations since it
runs in the idle thread TCB context. Declare the function with
the naked attribute, to ensure that the compiler always eliminates
the function prologue. Previously we rely on the -O2 optimization
flag for this, which on certain compilers (clang for instance) may
not guarantee that the function prologue gets eliminated.

Signed-off-by: Chang Liu <chang_liu3@brown.edu>
2021-08-30 10:46:12 +10:00
Gerwin Klein
f60875d3c0 fastpath: placate clang-11
clang-11 warns "converting the enum constant to a boolean". The
comparison generates the same code, since the expression can
be evaluated at compile time (I checked the objdump).

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-30 09:41:45 +10:00
Axel Heider
da0aad0330 make kernel device frame handling more generic
The structure actually describes kernel frames and not kernel devices.
In most of the cases a peripherals will fit into one page, but some can
need more pages. On some platform there are no kernel devices at all.
Provides the macro NUM_KERNEL_DEVICE_FRAMES as simple way to find out if
there are mapping that hides the corner cases. This eventually allows
implementing a generic handling even on RISC-V without much overhead, so
the hack for HiFive/Spike can be removed.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Axel Heider
cd54bc95e1 inline parameter definition
There is no need to create an explicit helper variable.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Axel Heider
a7d38353a7 use helper variable to avoid redundancy
Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Axel Heider
7bff9f4cd1 use BIT() macro instead of explicit shifts
As a side effect, the BIT() macro creates a word_t instead of an int,
so it can can handle even shift that exceed the int limits. This makes
the code more robust and provides the preferred coding pattern.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Axel Heider
0f7135aae4 arm: add sanity check for device mappings
Kernel device frames can never be executable. Even is this is generated
code, having an other assert here is a safe guard to catch potential
inconsistencies in the code generator.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Axel Heider
048c84fb94 use explicit field names in generated code
Using explicit field name in the assignment states more clearly what the
generated code does. It is also more robust and allows the compiler to
catch potential inconsistencies in case the structure details change.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Axel Heider
69204d0d2e trivial: break long lines in comment
Improve readability by breaking the line at around 80 chars.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Axel Heider
fc72f5e957 trivial: remove trailing empty lines
Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Axel Heider
3220f3016f trivial: add empty line after include guard
Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-27 21:15:11 +10:00
Gerwin Klein
f236ae8935 github: trigger main test on push to master
The trigger action sends repository_dispatch events to all
main test repositories of the manifests this repo is part of.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-27 14:08:23 +10:00
Axel Heider
43667a04f4 boot: print reserved and available memory regions
Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-25 18:15:38 +10:00
Gerwin Klein
7892335ca1 tools: more portable shell test
No need for bash style test `[[ .. ]]`, normal POSIX test `[ .. ]`
works fine.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-25 17:56:49 +10:00
Gerwin Klein
00879fa943 tools: use /usr/bin/env for bash/sh invocation
This implements GitHub PR #115 on the current repo state. /usr/bin/env
is already used for other (cmake/python/etc) invocations, and this PR
brings bash/sh into line with that for slightly improved portability.

Co-authored-by: Douglas Wilson <douglas.wilson@gmail.com>
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-25 17:56:49 +10:00
Gerwin Klein
7f562e1633 tools: consolidate RISC-V + Arm memory base logic
Co-authored-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Co-authored-by: Axel Heider <axel-h@users.noreply.github.com>
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-24 18:04:43 +10:00
Gerwin Klein
2296484665 tools: add risc-v dtb interrupt parsing
Co-authored-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-24 18:04:43 +10:00
Gerwin Klein
3398c01ee9 umm.py: no memoization
Memoization is not worth it here, the runtime of the entire program
is tiny. Removing the comment to curb temptations in the future.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-24 18:04:43 +10:00
Axel Heider
2836310f9a use ARRAY_SIZE to avoid implicit assumptions
MAX_NUM_FREEMEM_REG is used to define the number of elements of the
array ndks_boot.freemem[]. However, in the code iterating over the
elements, using the macro ARRAY_SIZE() is more straight forward and
avoids pulling in unnecessary dependencies.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-24 16:43:25 +10:00
Axel Heider
c72ecc7dd8 boot: reduce amount of helper functions
The python code generator ensures avail_p_regs always exists.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-24 16:14:26 +10:00
Axel Heider
b64e2deb3a boot: remove obsolete prototypes
Signed-off-by: Axel Heider <axelheider@gmx.de>
2021-08-24 16:14:26 +10:00
Gerwin Klein
02ddcd110a mcs: Remove domain time check from preemptionPoint
This removes the operations that trigger a reschedule or reprogram the
timer from `preemptionPoint` to ensure the relevant state updates in
the proof occur where they are easier to verify.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2021-08-24 10:22:33 +10:00
Axel Heider
f04c6c6378 risc-v/polarfire: set KernelOpenSBIPlatform
Signed-off-by: Axel Heider <axel.heider@hensoldt-cyber.de>
2021-08-24 10:04:56 +10:00
Axel Heider
d0a3b28005 risc-v: avoid warning about interrupt parsing
Avoid the warning 'WARNING:root:Not sure how to parse interrupts for
"/cpus/cpu@0/interrupt-controller"' when building for platform hifive.

Signed-off-by: Axel Heider <axel.heider@hensoldt-cyber.de>
2021-08-24 10:04:56 +10:00
Axel Heider
8f9fdd7b41 trivial: fix typo in log message
Signed-off-by: Axel Heider <axel.heider@hensoldt-cyber.de>
2021-08-24 10:04:56 +10:00
Axel Heider
fb6c7f143b trivial: fix typos in comment
Signed-off-by: Axel Heider <axel.heider@hensoldt-cyber.de>
2021-08-24 10:04:56 +10:00
Axel Heider
1a3bb0156c trivial: add space before operator
Signed-off-by: Axel Heider <axel.heider@hensoldt-cyber.de>
2021-08-24 10:04:56 +10:00
Axel Heider
f8d12311ba risc-v: don't add 8 bytes space at end of bss
The additional 8 byte go into a new page and then the rest of the page
is filled with padding. There is no good explanation what the 8 bytes
are used for, could be some copy/paste from another linker script.

Signed-off-by: Axel Heider <axel.heider@hensoldt-cyber.de>
2021-08-23 17:42:50 +10:00
Curtis Millar
ca34076c44 trivial: Consistent use of NODE_STATE fix
Fix some cases where `NODE_STATE` arguments were parenthesised in a
manner that was inconsistent with other uses (but also surprisingly
still valid?).

Signed-off-by: Curtis Millar <curtis@curtism.me>
2021-08-21 14:11:57 +10:00
Curtis Millar
96b8dca031 mcs: Don't check if old SC is still configured
When we are changing to a new SC, it doesn't matter whether the old SC
is still configured. We should also know statically within
switchSchedContext that whichever SC we will use to execute with next is
both present and configured.

As such, this check can be removed.

Signed-off-by: Curtis Millar <curtis@curtism.me>
2021-08-21 14:11:57 +10:00