Commit graph

1709 commits

Author SHA1 Message Date
Rafal Kolanski
c9989664e3 AArch64: mark isFpuEnable as DONT_TRANSLATE
Current verification model does not include lazy FPU switching, i.e. it
acts as if this function always returns true, so no FPU faults could be
produced. In order to guard against deriving a contradiction, we don't
allow the C parser to translate it.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2024-02-02 09:14:07 +11:00
Gerwin Klein
cc3205ea48 aarch64/vspace: simplify check for page PTE
- directly test for page PTE types instead of testing for invalid etc.

- remove unnecessary condition `resolve_ret.ptBitsLeft > PAGE_BITS`
  (always true).

- reduce bitfield accesses via pointers to make verification easier.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-01-22 14:58:49 +11:00
Gerwin Klein
7f4662a791 Revert "aarch64/vspace: allow flushing larger .."
This reverts commit 494dd2dd96.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-01-22 14:58:49 +11:00
Gerwin Klein
494dd2dd96 aarch64/vspace: allow flushing larger pages
- The failure condition `resolve_ret.ptBitsLeft > PAGE_BITS` prevented
  larger page sizes from being flushed in VSpaceRoot invocations.

  Instead of testing for number of bits left to resolve, simply check
  the PTE whether it is a page or not.

- reduce bitfield accesses via pointers to make verification a bit
  easier.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-01-22 11:29:04 +11:00
Gerwin Klein
4a2f8e7a81 aarch64 structures: constrain irq_w field width
The rest of the code uses 9-bit irq width. Keep in sync here to ease
verification.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-01-16 10:55:41 +11:00
Rafal Kolanski
55aee64707 arm hyp: gic_vcpu_num_list_regs should be word_t
On AArch64, if this is int, we encounter a situation where we can't
prove equivalence with the abstract spec without an extra invariant that
the number of these registers isn't zero (to satisfy 32<->64 bit casts).
Sticking with word size will make sense on both 32 and 64 bit.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-12-06 03:23:49 +11:00
Rafal Kolanski
66e5c79d06 Arm 64-bit: do not use unsigned int for arg length
Arch_decodeInvocation takes a word_t length and then passes it to
functions that take an unsigned int length. This was OK on 32-bit where
these types are the same, but on 64-bit this is a downcast without a
range check. It isn't clear why this doesn't trip a compiler warning.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-12-06 03:23:49 +11:00
Axel Heider
7d93471e9c debug: use c99 standard instead of gcc extensions
Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-11-16 12:09:52 +00:00
Ivan-Velickovic
49e5f47041 Update PLIC handling for Star64/U74-MC
Similarly to the U54-MC, the U74-MC has a S-core that does not run in
supervisor mode.

Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
2023-11-08 14:34:18 +00:00
Ivan-Velickovic
e959f83962 Add support for Star64 SBC
Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
2023-11-08 14:34:18 +00:00
Gerwin Klein
4b8bed320d arm_global: document deadline assert
The comment that PRECISION is too low when the assert fails was wrong.
PRECISION should have no influence on it.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-11-08 11:01:00 +11:00
Gerwin Klein
14ff0c28ec x86 setDeadline: must set at least 1 tick
- make sure the tick count does not underflow
- make sure the tick count does not become 0 in the division, because
  a value of 0 stops the timer.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-11-08 11:01:00 +11:00
Gerwin Klein
dac2857229 mcs: move setDeadline assertions
Move the ksCurTime assertions out of setDeadline, because they are not
necessarily true there. Assert ksCurTime in setNextInterrupt instead.

We only know that the deadline being set is at least ksCurTime -
getTimerPrecision(), which can be slightly in the past (ksCurTime is
already slightly in the past, at kernel entry).

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-11-08 11:01:00 +11:00
Michael McInerney
521f7e3c19 mcs: remove getKernelWcetTicks from refill_ready
Previously, a refill would be ready if its head time
was at most getKernelWcetTicks after the current time.
This would mean that refill_unblock_check could
bring a refill's time forward, which violates an
invariant (namely that the time of the last refill
is at most the period from the time of the head refill).

Moreover, since the time to exit the kernel is always
less than the WCET, this might result in us running
a thread whose refill time is in the future, which
seems to violate the timing model.

Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2023-11-08 11:01:00 +11:00
Gerwin Klein
97588df016
mcs: simplify sc_sporadic, assert invariant
It is an invariant in the MCS kernel that scSporadic implies sc_active.
Make use of that invariant by avoiding an explicit check for sc_active,
but assert the invariant in debug mode so it fails quickly when new
code breaks the invariant.

Essentially reverts 56098195f2 now that the invariant is preserved,
but adjusts the assertion from 17109eb8c9 to actually express
the invariant.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-11-07 08:39:10 +11:00
Hesham Almatary
c2497cbb38 riscv: place traps and fastpath code adjacently
Follow Arm's code where it tries to place traps and vector
code adjacently in a 4KiB page to optimise performance
(through spatial cache locality).

Closes #1091

Signed-off-by: Hesham Almatary <hesham.almatary@cl.cam.ac.uk>
2023-11-02 09:36:28 +00:00
Rafal Kolanski
4f9b736526 aarch64: use VS prefix for vspace_cap fields
The vspace (top level PT) cap had non-standard names which were a bit
confusing to reason about. The name conflict with capPTBasePtr also
spits out fully-qualified names in verification.
This commit updates all the field names of vspace_cap to start with
"capVS" and updates all the call sites.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-27 10:25:37 +11:00
Indan Zupancic
b4592ebc97
ARM: No special handling for edge-triggered IRQs
Clearing the pending state only has an effect if the IRQ state is
active-and-pending, which happens for edge-triggered interrupts if
another edge happens on the IRQ line for the currently active
interrupt. This window is small enough to ignore, at worst user
space will get another notification, which is harmless.

If unnecessary notifications are unwanted, the pending state should
be cleared during seL4_IRQHandler_Ack(), as that covers a much bigger
window. However, edge-triggered interrupts are not expected to happen
often. Making all interrupt handling slightly faster and the code
simpler is the better trade-off.

Reading the GIC config word is very slow for GICv2, see pull #1107.

Signed-off-by: Indan Zupancic <indan@nul.nu>
2023-10-26 11:34:51 +01:00
Rafal Kolanski
908cac7202 aarch64: IS_PAGE_ALIGNED -> checkVPAlignment
Verification sees macros as the preprocessed C code. On other arches, we
have checkVPAlignment, but on AArch64 we had IS_PAGE_ALIGNED only. Since
this was the only use, this commit also removes IS_PAGE_ALIGNED in
favour of checkVPAlignment.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-26 10:52:01 +11:00
Rafal Kolanski
88c35852fc aarch64: performASIDPoolInvocation consistency
For verification purposes, use same arg names as other platforms, and
don't go through `_ptr_set_` from the bitfield generator (same as
RISC-V).

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-26 10:52:01 +11:00
Nick Spinale
c49ed7c152 boot: skip clock sync test on qemu-arm-virt
This sanity check does not pass reliably on qemu-arm-virt due to it
being a virtualized platform.

Signed-off-by: Nick Spinale <nick@nickspinale.com>
2023-10-24 20:38:43 +11:00
Michael McInerney
6de399dc65 mcs: rephrase refill_capacity to ease verification
Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2023-10-24 08:43:03 +11:00
Rafal Kolanski
7221eba1b9 arm: tune vcpu/gic struct padding for verification
Verification requires packed C structures for reasoning. While we
previously updated `struct vcpu` to be packed on AArch32, on AArch64
`struct gicVCpuIface` needs extra padding.

This extra padding now aligns a previously un-aligned field on AArch32,
meaning that needs to go away, and the comment there adjusted.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-20 12:39:47 +11:00
Rafal Kolanski
a5cb1a86b4 aarch64: add MODIFIES for DONT_TRANSLATE ops
These were marked DONT_TRANSLATE due to 32-bit `__asm__` blocks which
verification can't handle, which resulted in MODIFIES proofs not being
generated.
This commit adds the obvious MODIFIES proofs for machine ops: nothing
gets modified by reading hardware registers, and writing them only
changes state that isn't in the model.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-19 00:01:07 +11:00
Kent McLeod
45bf84798c arm,smc: Handle revoke cap operations
Enable badged SMC capabilities to be revokable so that dynamic systems
can revoke badged capabilities that are handed out.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-27 11:44:51 +10:00
Alex Pavey
7d029e56e2 smc_cap: Add badge handling to smc cap
Signed-off-by: Alex Pavey <Alex.Pavey@dornerworks.com>
2023-08-27 11:44:51 +10:00
Alex Pavey
e62bc9bba3 smc_cap: Add SMC Capability with Call method
See PR at https://github.com/seL4/seL4/pull/701

Signed-off-by: Robbie VanVossen <robert.vanvossen@dornerworks.com>
2023-08-27 11:44:51 +10:00
Axel Heider
4d77c7008f boot: Remove constant BI_FRAME_SIZE_BITS
Use seL4_BootInfoFrameSizeBits directly.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-08-23 15:10:32 +02:00
Axel Heider
b8c0b1cb02 boot: introduce seL4_BootInfoFrameSize
Provide seL4_BootInfoFrameSize (and seL4_BootInfoFrameBits) for
userland, to there is no longer a need to hard-code the 4 KiByte
assumption.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-08-23 15:10:32 +02:00
Rafal Kolanski
8153bc569e aarch64: avoid void-return statements
C parser has issues with `return f(...)` when f's return type is void.
Rephrase `vcpu_hw_write_reg` to look like its AArch32 equivalent, using
`break` in the switch statement.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-08-22 18:36:05 +10:00
Rafal Kolanski
d06eb0a81a aarch64: DONT_TRANSLATE 32-bit __asm__
Verification infrastructure can only handle word-sized variable access
in __asm__ statements. The following functions use 32-bit access on a
64-bit arch and are now marked DONT_TRANSLATE:
* readCIDR
* writeCIDR
* readAFSR0
* writeAFSR0
* readAFSR1
* writeAFSR1
* readESR
* writeESR
* readISR
* vcpu_init_vtcr

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-08-22 18:36:05 +10:00
Axel Heider
aa118c25b8 use types time_t and tickts_t properly
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
2023-08-14 15:41:57 +10:00
Axel Heider
cbad541120 doc: improve comments
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
2023-08-14 15:41:57 +10:00
Axel Heider
1ca227a1b5 boot: simplify boot code recycling
Add helper functions to get kernel image location. This removes any
dependencies from the rest of the code on symbols and defines. It
also avoid passing a parameter though various functions.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-08-13 09:04:26 +10:00
Mathieu Mirmont
f2428d2b29 x86: include apic.h instead of xapic.h
Incuding apic.h also gets x2apic.h included.

Signed-off-by: Mathieu Mirmont <mat@parad0x.org>
2023-08-13 09:02:57 +10:00
Ivan-Velickovic
6904039608 Read time directly on RISC-V platforms
Currently getting the timestamp for RISC-V platforms uses the
`rdtime` pseudo-instruction which ends up invoking OpenSBI
and then accessing the CLINT memory-mapped `mtime` register.
This patch eliminates the use of `rdtime` in favour of
directly getting the timestamp for performance.

Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
2023-08-13 09:01:48 +10:00
Kent McLeod
cb8ee83f0c aarch64,vspace: Remove pud cap type
Now the vspace_cap is used for all vspace roots and all other page
tables are referred to by page table caps.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-10 08:20:22 +10:00
Kent McLeod
dc808b3d76 aarch64,vspace: Rename pgd cap to vspace cap
This is already what's presented at userlevel. Now the underlying kernel
cap reflects the same name.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-10 08:20:22 +10:00
Kent McLeod
b3cc852425 aarch64,vspace: Remove page_directory captype
The page_table cap is used in it's place.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-10 08:20:22 +10:00
Kent McLeod
5b00dff656 aarch64,vspace: Merge pgde_t type into pte_t type
Finish combining different page table types into a single type.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-10 08:20:22 +10:00
Kent McLeod
fc4ee3f931 aarch64,vspace: Merge pude_t type into pte_t
Next step is to merge pude_t type.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-10 08:20:22 +10:00
Kent McLeod
dad370959f aarch64,vspace: Merge pde_t into pte_t
Remove the pde_t type and replace all usages with pte_t.
This doesn't remove the page directory cap type yet. Now the page
directory cap refers to a table of pte_t entries and is treated the same
as the object that a page table cap refers to.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-10 08:20:22 +10:00
Kent McLeod
629c60d0a0 aarch64,vspace: Setup single pte_t type
This first commit only handles 4k pages.
4k pages are mapped using level 3 descriptor formats which annoyingly
have an opposite type definition (bit[1]) from all other levels. At all
other levels, a bit value of 0 is page and 1 is table. At level 3, a bit
value of 1 is page (and there is no bit value for a table).

This prevents us from using a single tagged-union type definition for
all page table descriptor definitions. For now we treat 4k pages as
special and try and push on ahead with the single type definition
anyway.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-10 08:20:22 +10:00
Axel Heider
3c180701ee remove Arch_migrateTCB()
It does the same on all architectures, so the contents can be moved
into the generic code.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-06-21 08:58:28 +10:00
Axel Heider
5091e5313d doc: fix typos
Co-authored-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-06-08 12:47:14 +10:00
Kent McLeod
7fec9bc9e9 Add CONFIG_X86_64_VTX_64BIT_GUESTS guards
Guard the new implementation of 64-bit x86 guests behind a config
option. This is done so that existing projects that use x86_64 hosts
with ia32-bit guests can continue to be supported until either the old
feature is preferred to be deprecated, or support can be added to
support both simmultaneously.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-06-06 13:29:34 +10:00
Chris Guikema
2dbd1b818a 64-bit-vms: Add kernel support for 64-bit VMs
This commit combines a number of smaller commits which do the following:

    * Enter IA-32e mode when running a 64-bit host
    * Handle additional general purpose registers in 64-bit mode
    * Handle 64-bit specific MSR events
    * Properly save and restore FS, GS, and Shadow GS registers

CCDC-GVSC DISTRIBUTION A.  Approved for public release; distribution
unlimited. OPSEC#4481.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-06-06 13:29:34 +10:00
Gerwin Klein
35c41a822f macros: avoid breaking C subset
__builtin_offsetof is not part of the verification C subset -- avoid
accidental use by not declaring a macro for it and filter out the
single use by explicitly marking it as invisible to verification.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-05-31 14:55:57 +10:00
Gerwin Klein
94d393418e gic_v3: _Static_assert is not supported
Prefer compile_assert over _Static_assert. The latter is only available
in C11, and the verification demands C99.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-05-31 13:30:07 +10:00
JorgeMVP
b544529615 generc_timer: enable only once for mcs/non-mcs
Enable the timer only at initialization and since it is always
enabled. It is not needed to be re-enabled.

Signed-off-by: JorgeMVP <jorgepereira89@gmail.com>
2023-05-25 20:42:02 +10:00