Commit graph

1728 commits

Author SHA1 Message Date
milicat
d3d4cc6023 Fix macro to get irq idx from irqt
Signed-off-by: milicat <milicat@foxmail.com>
2024-06-25 22:18:54 +10:00
Michael McInerney
b93de1fdd5 mcs: use sc_active in isSchedulable
Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2024-06-22 18:06:05 +10:00
Andy Bui
c7bdf1f921 vcpu: only trap WFx instructions from vCPUs
When KernelArmDisableWFIWFETraps is disabled (trapping of WFI/WFE is
enabled), the kernel traps WFx instructions from both native and vCPU
threads. This change makes the code in line with the config description.

In any case, there don't exist many use cases for trapping WFx from
native threads vs vCPU threads. Example: kvm uses this to yield physical
CPU time to other vCPUs instead of busy waiting.

Signed-off-by: Andy Bui <andy.bui2001@gmail.com>
2024-06-20 14:36:32 +10:00
Gerwin Klein
6e9370a561 ioapic: set IOAPIC_IRQ_LINES to max allowed
Correctly mask the IOAPICVER register to the Maximum Redirection Entry
field to potential avoid spurious higher bits on e.g. AMD processors.

Set IOAPIC_IRQ_LINES to the maximum value this field is allowed to
return (239+1). While our haswell machines report 24 IRQ lines as
expected, the skylake machines report 120.

The only impact should be the size of the ioredtbl_state array.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-06-14 14:19:24 +10:00
Axel Heider
503ad776bc risc-v: improve comments
- mention skipped t1/x6
- mention skipped a0/x10, a1/x11

Signed-off-by: Axel Heider <axel.heider@codasip.com>
2024-05-23 15:48:04 +01:00
Michael McInerney
686bba4d2a mcs: more uniformly handle ready and release queue
This introduces library functions for updating the linked lists which
use the tcbSchedNext and tcbSchedPrev pointers of a TCB, and uses these
to perform the updates to the ready queues and the release queue.

In order to accommodate this, ksReleaseQueue is now of type tcb_queue_t.

Co-authored-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2024-05-23 18:04:06 +10:00
wucke13
0260fba168 fix: invisible chars due to ANSI escape codes
The prior behavior would emit ANSI escape codes which set the terminal
foreground color to black bold (`[30;1m`), leaving the default
background color. On many terminals configured with a dark color scheme,
this creates black on black characters, i.e. the output is invisible.

This change moves to a better adapted output, where the output is only
marked as bold (`[1m]`), which works well on all color schemes.

Fixes #1243

Signed-off-by: wucke13 <wucke13@gmail.com>
2024-04-28 10:26:11 +10:00
Axel Heider
a58480425c make SMP conditional check more general
Check for CONFIG_ENABLE_SMP_SUPPORT instead of checking for the
number in CONFIG_MAX_NUM_NODES. This allows enabling SMP support
with just one node also.

Signed-off-by: Axel Heider <axel.heider@codasip.com>
2024-04-11 09:20:00 +01:00
Axel Heider
05d0f06620 fix type, add missing 'extern' keyword
Signed-off-by: Axel Heider <axel.heider@codasip.com>
2024-04-09 19:55:34 +01:00
Krishnan Winter
90bd5575b2 aarch64: Rename armKSGlobalLogPDE
Renamed armKSGlobalLogPDE to
armKSGlobalLogPTE inline with RFC-10.

Signed-off-by: Krishnan Winter <krishnanwinter1@gmail.com>
2024-04-09 09:35:54 +01:00
Krishnan Winter
21d699828d Fix macro to access overflow node
Previously accessing the ccnt_num_overflows
value using the NODE_STATE macro. In SMP
configurations, this looks for this value
in the system node state, however, it
resides in the cpu arch node state. This should
therefore be accessed using the ARCH_NODE_STATE.

Signed-off-by: Krishnan Winter <krishnanwinter1@gmail.com>
2024-03-27 10:57:45 +00:00
Axel Heider
271f6cc903 risc-v: make trap_entry a function
Signed-off-by: Axel Heider <axelheider@gmx.de>
2024-03-23 08:48:42 +11:00
Axel Heider
ff422899fc trivial: remove superfluous empty line
Signed-off-by: Axel Heider <axelheider@gmx.de>
2024-03-23 08:48:42 +11:00
Birgit Brecknell
f6656e2c78 Add a glossary to the manual
Add a glossary with seL4-specific terms and their
definitions.
Remove chapter number from bibliography
Tweak Makefile for glossary

Signed-off-by: Birgit Brecknell <bbrcknl@gmail.com>
2024-03-20 14:54:06 +11:00
Indan Zupancic
b527b46dec Arm32: Fix vcpu_hw_write_reg
Forgotten in commit 5bce5c0c1e.

Signed-off-by: Indan Zupancic <indan@nul.nu>
2024-03-15 19:27:37 +01:00
Gerwin Klein
4172bd6170
vcpu: add padding to keep vcpu struct packed
Add padding to keep vcpu struct packed on 32-bit platforms. This doesn't
change the size on 32-bit platforms, because the compiler would insert
padding itself. It does increase the size of the struct by one word
on 64-bit platforms, but it remains below 2^vcpuBits.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-03-14 10:02:43 +01:00
Kent McLeod
5bce5c0c1e
ARM: Allow VMPIDR_EL2 reg to be set on unicore
Currently the seL4_VCPUReg enum only defines the seL4_VCPUReg_VMPIDR_EL2
register when the kernel is configured for SMP. This register should be
available for unicore systems too as otherwise a user level VMM is not
able to control the value of MPIDR_EL1 that the guest VM reads.

Signed-off-by: Kent McLeod <kent@kry10.com>
2024-03-14 10:02:42 +01:00
Indan Zupancic
3ccbfc083a RISC-V SMP: Fix Compile Error
Partially revert commit 70d1a5f792.

Can't include arch/machine.h because that will cause
a circular include dependency.

Signed-off-by: Indan Zupancic <indan@nul.nu>
2024-03-13 19:19:39 +01:00
Axel Heider
70d1a5f792 riscv: add read_sscratch()
Signed-off-by: Axel Heider <axelheider@gmx.de>
2024-03-13 11:38:24 +00:00
Rafal Kolanski
c9989664e3 AArch64: mark isFpuEnable as DONT_TRANSLATE
Current verification model does not include lazy FPU switching, i.e. it
acts as if this function always returns true, so no FPU faults could be
produced. In order to guard against deriving a contradiction, we don't
allow the C parser to translate it.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2024-02-02 09:14:07 +11:00
Gerwin Klein
cc3205ea48 aarch64/vspace: simplify check for page PTE
- directly test for page PTE types instead of testing for invalid etc.

- remove unnecessary condition `resolve_ret.ptBitsLeft > PAGE_BITS`
  (always true).

- reduce bitfield accesses via pointers to make verification easier.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-01-22 14:58:49 +11:00
Gerwin Klein
7f4662a791 Revert "aarch64/vspace: allow flushing larger .."
This reverts commit 494dd2dd96.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-01-22 14:58:49 +11:00
Gerwin Klein
494dd2dd96 aarch64/vspace: allow flushing larger pages
- The failure condition `resolve_ret.ptBitsLeft > PAGE_BITS` prevented
  larger page sizes from being flushed in VSpaceRoot invocations.

  Instead of testing for number of bits left to resolve, simply check
  the PTE whether it is a page or not.

- reduce bitfield accesses via pointers to make verification a bit
  easier.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-01-22 11:29:04 +11:00
Gerwin Klein
4a2f8e7a81 aarch64 structures: constrain irq_w field width
The rest of the code uses 9-bit irq width. Keep in sync here to ease
verification.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-01-16 10:55:41 +11:00
Rafal Kolanski
55aee64707 arm hyp: gic_vcpu_num_list_regs should be word_t
On AArch64, if this is int, we encounter a situation where we can't
prove equivalence with the abstract spec without an extra invariant that
the number of these registers isn't zero (to satisfy 32<->64 bit casts).
Sticking with word size will make sense on both 32 and 64 bit.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-12-06 03:23:49 +11:00
Rafal Kolanski
66e5c79d06 Arm 64-bit: do not use unsigned int for arg length
Arch_decodeInvocation takes a word_t length and then passes it to
functions that take an unsigned int length. This was OK on 32-bit where
these types are the same, but on 64-bit this is a downcast without a
range check. It isn't clear why this doesn't trip a compiler warning.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-12-06 03:23:49 +11:00
Axel Heider
7d93471e9c debug: use c99 standard instead of gcc extensions
Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-11-16 12:09:52 +00:00
Ivan-Velickovic
49e5f47041 Update PLIC handling for Star64/U74-MC
Similarly to the U54-MC, the U74-MC has a S-core that does not run in
supervisor mode.

Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
2023-11-08 14:34:18 +00:00
Ivan-Velickovic
e959f83962 Add support for Star64 SBC
Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
2023-11-08 14:34:18 +00:00
Gerwin Klein
4b8bed320d arm_global: document deadline assert
The comment that PRECISION is too low when the assert fails was wrong.
PRECISION should have no influence on it.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-11-08 11:01:00 +11:00
Gerwin Klein
14ff0c28ec x86 setDeadline: must set at least 1 tick
- make sure the tick count does not underflow
- make sure the tick count does not become 0 in the division, because
  a value of 0 stops the timer.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-11-08 11:01:00 +11:00
Gerwin Klein
dac2857229 mcs: move setDeadline assertions
Move the ksCurTime assertions out of setDeadline, because they are not
necessarily true there. Assert ksCurTime in setNextInterrupt instead.

We only know that the deadline being set is at least ksCurTime -
getTimerPrecision(), which can be slightly in the past (ksCurTime is
already slightly in the past, at kernel entry).

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-11-08 11:01:00 +11:00
Michael McInerney
521f7e3c19 mcs: remove getKernelWcetTicks from refill_ready
Previously, a refill would be ready if its head time
was at most getKernelWcetTicks after the current time.
This would mean that refill_unblock_check could
bring a refill's time forward, which violates an
invariant (namely that the time of the last refill
is at most the period from the time of the head refill).

Moreover, since the time to exit the kernel is always
less than the WCET, this might result in us running
a thread whose refill time is in the future, which
seems to violate the timing model.

Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2023-11-08 11:01:00 +11:00
Gerwin Klein
97588df016
mcs: simplify sc_sporadic, assert invariant
It is an invariant in the MCS kernel that scSporadic implies sc_active.
Make use of that invariant by avoiding an explicit check for sc_active,
but assert the invariant in debug mode so it fails quickly when new
code breaks the invariant.

Essentially reverts 56098195f2 now that the invariant is preserved,
but adjusts the assertion from 17109eb8c9 to actually express
the invariant.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2023-11-07 08:39:10 +11:00
Hesham Almatary
c2497cbb38 riscv: place traps and fastpath code adjacently
Follow Arm's code where it tries to place traps and vector
code adjacently in a 4KiB page to optimise performance
(through spatial cache locality).

Closes #1091

Signed-off-by: Hesham Almatary <hesham.almatary@cl.cam.ac.uk>
2023-11-02 09:36:28 +00:00
Rafal Kolanski
4f9b736526 aarch64: use VS prefix for vspace_cap fields
The vspace (top level PT) cap had non-standard names which were a bit
confusing to reason about. The name conflict with capPTBasePtr also
spits out fully-qualified names in verification.
This commit updates all the field names of vspace_cap to start with
"capVS" and updates all the call sites.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-27 10:25:37 +11:00
Indan Zupancic
b4592ebc97
ARM: No special handling for edge-triggered IRQs
Clearing the pending state only has an effect if the IRQ state is
active-and-pending, which happens for edge-triggered interrupts if
another edge happens on the IRQ line for the currently active
interrupt. This window is small enough to ignore, at worst user
space will get another notification, which is harmless.

If unnecessary notifications are unwanted, the pending state should
be cleared during seL4_IRQHandler_Ack(), as that covers a much bigger
window. However, edge-triggered interrupts are not expected to happen
often. Making all interrupt handling slightly faster and the code
simpler is the better trade-off.

Reading the GIC config word is very slow for GICv2, see pull #1107.

Signed-off-by: Indan Zupancic <indan@nul.nu>
2023-10-26 11:34:51 +01:00
Rafal Kolanski
908cac7202 aarch64: IS_PAGE_ALIGNED -> checkVPAlignment
Verification sees macros as the preprocessed C code. On other arches, we
have checkVPAlignment, but on AArch64 we had IS_PAGE_ALIGNED only. Since
this was the only use, this commit also removes IS_PAGE_ALIGNED in
favour of checkVPAlignment.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-26 10:52:01 +11:00
Rafal Kolanski
88c35852fc aarch64: performASIDPoolInvocation consistency
For verification purposes, use same arg names as other platforms, and
don't go through `_ptr_set_` from the bitfield generator (same as
RISC-V).

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-26 10:52:01 +11:00
Nick Spinale
c49ed7c152 boot: skip clock sync test on qemu-arm-virt
This sanity check does not pass reliably on qemu-arm-virt due to it
being a virtualized platform.

Signed-off-by: Nick Spinale <nick@nickspinale.com>
2023-10-24 20:38:43 +11:00
Michael McInerney
6de399dc65 mcs: rephrase refill_capacity to ease verification
Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2023-10-24 08:43:03 +11:00
Rafal Kolanski
7221eba1b9 arm: tune vcpu/gic struct padding for verification
Verification requires packed C structures for reasoning. While we
previously updated `struct vcpu` to be packed on AArch32, on AArch64
`struct gicVCpuIface` needs extra padding.

This extra padding now aligns a previously un-aligned field on AArch32,
meaning that needs to go away, and the comment there adjusted.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-20 12:39:47 +11:00
Rafal Kolanski
a5cb1a86b4 aarch64: add MODIFIES for DONT_TRANSLATE ops
These were marked DONT_TRANSLATE due to 32-bit `__asm__` blocks which
verification can't handle, which resulted in MODIFIES proofs not being
generated.
This commit adds the obvious MODIFIES proofs for machine ops: nothing
gets modified by reading hardware registers, and writing them only
changes state that isn't in the model.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-10-19 00:01:07 +11:00
Kent McLeod
45bf84798c arm,smc: Handle revoke cap operations
Enable badged SMC capabilities to be revokable so that dynamic systems
can revoke badged capabilities that are handed out.

Signed-off-by: Kent McLeod <kent@kry10.com>
2023-08-27 11:44:51 +10:00
Alex Pavey
7d029e56e2 smc_cap: Add badge handling to smc cap
Signed-off-by: Alex Pavey <Alex.Pavey@dornerworks.com>
2023-08-27 11:44:51 +10:00
Alex Pavey
e62bc9bba3 smc_cap: Add SMC Capability with Call method
See PR at https://github.com/seL4/seL4/pull/701

Signed-off-by: Robbie VanVossen <robert.vanvossen@dornerworks.com>
2023-08-27 11:44:51 +10:00
Axel Heider
4d77c7008f boot: Remove constant BI_FRAME_SIZE_BITS
Use seL4_BootInfoFrameSizeBits directly.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-08-23 15:10:32 +02:00
Axel Heider
b8c0b1cb02 boot: introduce seL4_BootInfoFrameSize
Provide seL4_BootInfoFrameSize (and seL4_BootInfoFrameBits) for
userland, to there is no longer a need to hard-code the 4 KiByte
assumption.

Signed-off-by: Axel Heider <axelheider@gmx.de>
2023-08-23 15:10:32 +02:00
Rafal Kolanski
8153bc569e aarch64: avoid void-return statements
C parser has issues with `return f(...)` when f's return type is void.
Rephrase `vcpu_hw_write_reg` to look like its AArch32 equivalent, using
`break` in the switch statement.

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-08-22 18:36:05 +10:00
Rafal Kolanski
d06eb0a81a aarch64: DONT_TRANSLATE 32-bit __asm__
Verification infrastructure can only handle word-sized variable access
in __asm__ statements. The following functions use 32-bit access on a
64-bit arch and are now marked DONT_TRANSLATE:
* readCIDR
* writeCIDR
* readAFSR0
* writeAFSR0
* readAFSR1
* writeAFSR1
* readESR
* writeESR
* readISR
* vcpu_init_vtcr

Signed-off-by: Rafal Kolanski <rafal.kolanski@proofcraft.systems>
2023-08-22 18:36:05 +10:00