For some reason the kernel documented and maintained constants for a
512MiB 'huge page' in riscv32 which is not part of the specification.
The references and constants are removed
Explicitly create a struct definition for irq_t on SMP Arm
configurations. This makes it a lot harder to mistakenly use the wrong
irq encoding when moving an irq between a cnode index and hardware irq
number / core. A couple areas where this was being handled incorrectly
was fixed as part of the refactor. When performing an ipi for masking
PPI interrupts, the idx encoding is used as it fits into a single word.
Every platform has to implement a standard set of interrupt interfaces
that the kernel uses to interract with a machine's interrupt controller.
Providing a single header file for each of these functions provides a
single location to document their behavior.
Both the private and global arm timers are clocked from the same source
and neither of the drivers apply a pre-scaler so the frequency should be
the same in both configurations.
The frequency of this clock is based on PLL1 which could potentially lie
anywhere in the range of 650MHz to 1.3GHz. The value determined for MCS
appears to correctly agree with the user-level timer which appears to be
correctly implemented.
The DTS in the 'tools' directory is missing information about the EPIT2
timer. We add the entry into the corresponding overlay DTS file so that
the EPIT2 node will be included into the resulting DTB.
The corrected user timer showed that the estimated value for the kernel
timer used in MCS was incorrect. It has been re-calculated on the fixed
user-level timer.
According to the implementation of the user-level timer the primary
clock source (`m_clock`) can only be configured to 12MHz on TX1 and TK1
(see the comment in `libplatsupport` at
util_libs/libplatsupport/src/mach/nvidia/timer.c:213).
This should allow the TX1 to pass all MCS tests.
Currently the vcpu_switch function is called in the setVMRoot function
after possible early returns. In order to make sure the vcpu is
always switched, the call is moved into Arch_switchToThread before the
call to setVMRoot.
...and other tweaks.
* Clarify the synonymy of Receive and Wait on non-MCS systems.
* Note that Receive takes a reply object on MCS systems, and not on
non-MCS systems. Also note redundancy of Wait on non-MCS systems.
* Use the full English word "Receive" when the discussion is at the
conceptual level. It still gets abbreviated in C context, where it also
receives the "seL4_" prefix.
* Try a little harder to explain what's the same and what's different
about a non-MCS "reply capability" and an MCS capability to a reply
object.
* Explain what MCS stands for at the beginning of the chapter. In the
manual's current organisation, this precedes by a few paragraphs the
term's first occurrence.
* Recast language about things being "on the MCS kernel" in favour of
describing "MCS" and "non-MCS" _configurations_ of the kernel. (We do
not refer to the "master" kernel in the manual--thankfully.)
* Correct doubled word "to to".
* Italicise "reply capability" to better distinguish it from the
(already italicised) "reply object".
* Add a TODO comment about hyphenation grief.
* Recast language of introduction to system calls.
* Rearrange system calls to present them in a more pedagogically useful
order.
* Add TODO comment for future manual organisation efforts.
This sets the first UART as the stdout-path dts setting in the
"chosen" node in the HiFive device tree.
Change-Id: Icb6b9abf999bdd8a278df5a2ba73ad492af06a24
Other declarations of `userSize` give it the type `word_t`. Since proofs
use a mangled name that includes the type, giving `userSize` different
types at different locations occasionally breaks proofs.
Translation validation reports errors using the "real" struct type name
instead of the typedef name, so having anonymous structs makes debugging
translation validation harder.
When the FPU state is loaded from a thread for the first time the
uninitialised floating point exception register is 0 leading to the FPU
being disabled until an instruction fault occurs in that thread upon
re-entry.
Clearly, if we are loading the FPU state for a thread we want the FPU to
be enabled so we enable it whenever it is loaded.
This change broadens the caching of the FPU enable/disable bit from arm
to all platforms to ensure that on x86 time is not wasted on the
fastpath disabling or enabling an already disabled/enabled FPU.
The bootinfo extra size region is rounded up to a power of 2 size before
being mapped into the initial threads address space. This wasn't being
handled correctly which lead to a situation where if the bootinfo
finishes on the last address of a page table but the extra region size
is not a power of 2 size then there won't be a page directory allocated
where one needs to be and the kernel would crash.
This function returns the size_bits for an allocation covering the size
of the extra boot info region.
Previously it was incorrectly handling rounding up the result of CLZL.
The elfloader is going to start using devices based on the device tree.
Add an output method for hardware_gen.py that generates header files
that the elfloader can use. Currently they contain an array of
"devices", where each device has a compatiblity string and a series of
regions (represented simply as the physical address of the region).
For now, the elfloader only uses the serial device specified by the
stdout-path property in the DTB.
With the prescaler set the frequency would be 24MHZ/2.
In order to synchronise with the timer in platsupport for mcs,
both require a 24MHZ freq. Hence this commit turns prescaling
off in the kernel. Kernel timers should accurately timeout test
1 second now. Previously it was running too fast, around half a second.
This change introduces a `gcc` hunting helper function to `gcc.cmake` in
order to help us find an appropriately prefixed `gcc` for the target
being built for. We use this helper to find 32b ARM cross-compiling
`gcc`s for both Debian and Red Hat based distros.
Relates to #168. The definition for `seL4_UntypedRetypeMaxObjects` lives
in the UAPI `types.h` but appears to have no link to the value actually
used by the kernel, which is configurable. This change sets the UAPI
definition to the generated definition from the kernel config steps and
defaults to the previous fixed value if, for some reason, the configured
definition is not available.
Recast introductory paragraphs to better describe the document and
characterise the intended audience.
Move information intended for document maintainers and kernel engineers
to a comment. Add guidance for engineers so they better know when and
how to update this document. (Thanks to Kent for the discussion!)
The `docs/sel4_release` page is not a set of release notes per se, more
like a feature grid and release history; describe it differently.
Style document title as a top-level heading.
These changes need to be reverted until we can properly test the changes
with all of our hardware online (currently we cannot test on x86
hardware).
This reverts commit a0aeec3b304d16909619bc847197df221c73a0c4.
This reverts commit af0fdc82c23f1e7e3f1e568f6987f5afd0d2150a.
This reverts commit a190a14ecaae688a6b40dd0a699b8f49c2c0631e.
When the FPU state is loaded from a thread for the first time the
uninitialised floating point exception register is 0 leading to the FPU
being disabled until an instruction fault occurs in that thread upon
re-entry.
Clearly, if we are loading the FPU state for a thread we want the FPU to
be enabled so we enable it whenever it is loaded.
This change broadens the caching of the FPU enable/disable bit from arm
to all platforms to ensure that on x86 time is not wasted on the
fastpath disabling or enabling an already disabled/enabled FPU.
Ariane platform doesn't have any kernel devices. But the DTS parser
doesn't accept empty properties. Removing it completely to avoid DTS
parsing error.
