Curtis Millar 5646f77463 RFC-3: Update user context for ARM with thread IDs ... Switched appropriate naming conventions. Was using the aarch64, have switched to aarch64 names. TIPDRURW -> tpidr_el0 TPIDRURO -> tpidrro_el0 TPIDRPRW -> tpidr_el1 Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so that it can be written to from user-land. Thread ID registers tpidr_el0 have been added to the user context for aarch32 and aarch64. Only the thread ID that is writeable from EL0 is saved in the TCB and saved/restored on context switch. Thread IDs that are only changed within a VM (the read-only thread ID for exception level 0 and the thread ID for exception level 1) are stored in the VCPU and saved and stored as part of VM enable/disable. Thread IDs that are only changed with VMs have been separated out into hypervisor code.		2019-07-01 11:00:37 +10:00
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sel4arch.xml	RFC-3: Update user context for ARM with thread IDs	2019-07-01 11:00:37 +10:00