Uplift Hexagon architecture to RzIL
The general structure is, that every (sub-)instruction has a getter for it's RzIL code.
Calling the getter will return the RzIL operation.
If RzIL for an instruction is requested, the plugin makes a decision. Because Hexagon only executes whole instruction packets. If the instruction is not the last instruction in a packet, it will simply return `EMPTY()`. If the RzIL for the last instruction in a packet is requested, it will get the RzIL operations for all instructions in the packet, shuffles them into the correct execution order (according to some rules) and returns the complete operation for the packet.
The RzIL code was entirely generated with the [rzil-compiler](https://github.com/Rot127/rzil-compiler/), using the semantic definition of the [QEMU Hexagon module](https://github.com/qemu/qemu/tree/master/target/hexagon).
Currently successful compile instructions (and tested):
```
[*] 1581/1733 standard instructions compiled.
[*] 431/643 HVX instructions compiled.
[*] In total: 2012/2376 instructions compiled.
```
It was tested with:
- (Semantic tests) `rz-tracetest` against the execution trace of the QEMU Hexagon test binaries.
- (Bug free and semi-semtantic test) Adding tests which simply execute the test binaries to ensure leak and segfault free execution. Also it is executed until a certain instruction is reached (end of `main` or `loc.pass` symbol), partially testing it executes correctly.
For the uplifting several changes and modernization had to be made:
- Enhance consistency of decoding
- Allow to disassemble an instruction without copying the result. This is used if the given buffer of instruction bytes is larger than one instruction width. In this case, as many instructions as the buffer can hold are disassembled and buffered for later.
- Generally enhance buffering of instructions.
- Allow to mark a packet as valid before it is completely decoded (in case we know it must be valid, e.g. if it is a jump target of a valid packet).
- Fix (hopefully) all memory leaks of the Hexagon plugin.
- Changes to register getters, because RzIL needs finer control to translate alias or explicit register names to their real register.
- Getter for register name is now done by table, so for future distinction between DSP version we can just select another table.
- Translation functions from register alias or explicit name to their real register.
- Each operand contains now it's variable ID (e.g. `d` for register `Rd`) as in the ISA (for mapping in the RzIL code).
- Ease debugging by tracking in more precision, if an instruction is added to a stale, active or new packet.
- Add registers `C20` - `C29` (not yet present in LLVM)
- Some renaming to make the code more readable.
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