Squash of rizinorg/rizin PR #6434 ("improve TMS320C55x+ analysis and RzIL")
rebased onto dev, with the PR head's doubled c55plus_il.c (every symbol defined
twice, failing to compile) de-duplicated to a single clean copy.
Substantially extends the C55x/C55x+ RzIL lifter over the existing structured-
operand helpers: mov/copy (immediate, register, memory load/store, half-register
read-modify-write), the full addressing-mode set with post-modify side effects,
control and system-register moves, 40-bit accumulator ALU with shifted sources,
16-bit and dual-memory add/sub, the ST0_55 status-flag model (cmp/cmpand/rol/ror,
named-bit bset/bclr), a documented psh/pop stack model, address-unit amov/aadd/
asub and amar, and bcc/callcc control transfer. The multiply/MAC family and satr
are lifted with explicit, documented integer-mode approximations (not verified
DSP semantics); irreducibly multi-output primitives (bit counts, Viterbi, FIR,
distance) are left correct-or-NULL. The register file covers ac0-7 and xar, found
by validating on real Motorola Wrigley C55x+ firmware whose prologues save 40-bit
accumulators as dbl(acN)+acN.g pairs.
Adds RzIL-VM emulation tests (including the C55x and C55x+ _decrypt emulateme
binaries), per-instruction IL assertions, and ~95% instruction-class disassembly
coverage per corpus; pins little-endian in the VM tests for big-endian hosts; and
regenerates the analysis expectations against current dev.
Add a new LGPL-3.0 VAX-11 architecture plugin that replaces the removed
binutils-derived GPL one. It is written from scratch from the documented
VAX operand-specifier encoding and does not reuse any GPL code.
* hash: add chi-square (vs uniform) rz-hash plugin
Adds a chi-square goodness-of-fit (vs a uniform byte distribution)
statistic as an rz-hash plugin and the rz_hash_chisquare() API.
Unlike Shannon entropy, chi-square separates high-entropy data that is
truly uniform (encryption/CSPRNG, ~255) from high-entropy data that is
merely compressed or packed (much larger values), which is a common
question when triaging firmware blobs.
* hash: add index-of-coincidence rz-hash plugin
Adds the index of coincidence as an rz-hash plugin and the
rz_hash_ioc() API. IoC is ~1/256 for uniform data and markedly higher
for text, padding, single-byte-XOR'd data and repeating-key regions;
computed at several strides it is the Friedman/Kasiski test for a
repeating-XOR period.
* hash: add min-entropy rz-hash plugin
Adds min-entropy H_inf = -log2(max_i p_i) as an rz-hash plugin and the
rz_hash_min_entropy() API. This is the conservative worst-case entropy
used by NIST SP 800-90B: 8.0 for a uniform block, dropping as soon as a
single byte value dominates.
* hash: add serial-correlation rz-hash plugin
Adds the lag-1 serial correlation coefficient (with wrap-around, as in
the classic `ent` tool) as an rz-hash plugin and the
rz_hash_serial_correlation() API. Near 0 for compressed/encrypted data
but clearly non-zero for executable code, counters and gradients - the
order-aware axis that the histogram-only metrics cannot see.
---------
Co-authored-by: Anton Kochkov <anton.kochkov@gmail.com>
* Add ht benchmarks
* Initial implementation
* Finalize native per-group lookup support
* Lookup SSE2 implementation
* Improve hashing
* Add support for custom elem_size
* Avoid double h2 hashing when reserving slot
* Make custom elem_size support conditional
* Fix issues with bitwise and default lookup implementations
* Implement deletion trick optimization
* Track growth_size instead of deleted_slots
* Refactor SDB to access ht via API instead of internals
* Modify SDB tests which rely on hashtable order
* Fix SDB build warnings
* Fix bug with finding next power of two
* foreach_kv to return a bool result
* Change SDB diff order expected by serialize_analysis unit test
* Fix bug in the bitwise lookup implementation
* Remove second call to rz_core_init() which causes memory leaks
* Update some regression tests to accept reordered output
* Adapt ht clear to new implementation
* Use fini_kv_pair and fix 1 potential leak on malloc failure
* Fix cmd/types test after merge
* Avoid second call to calsize_key and avoid iter leaks on malloc failure
* Improve hash distribution
* Extend benchmark suite
* Fix bug with string hashing
* Branchless write to mirrored ctrl bytes
* Simplify string hash and remove potential UB
* Move RZ_PREFETCH macro to rz_types.h
* Add SSE2 discovery in Meson
* Forward SDB string hash function to ht string hash
* Try to revert test_cpu_profiles() to avoid relying on a baked SDB file
* Revert SDB/CDB hash function change
* Fix SDB reference to HT hash function instead of CDB hash
* Change calloc to malloc
* Avoid storing/checking key_len and key_value if they are ut64
* Improve string hash function
* Rename default hash functions
* Improve bench code
* linter.yml: set clang-path to point to llvm-18
* add h8/500 plugin stub
* refactor h8500 instruction parsing and disassembly logic
* fix: remove debug print statement from h8500 EA parsing
fix: correct plugin name from h8300 to h8500
add: new test case for h8500 disassembly
* refactor: improve operand parsing and disassembly logic for h8500
* refactor: update operand representation in h8500 EA parsing
* refactor: enhance operand definitions and add test cases for h8500 instructions
* fix: add h8500 disassembly plugin to command lists
* refactor: enhance H8500 instruction and operand structures for better parsing
* refactor: update H8500 instruction set with size suffixes and enhance operand handling
* Apply suggestion from @Copilot
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
* Apply suggestion from @Copilot
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
* refactor: update H8500 operand handling and address mode definitions for consistency
* refactor: update H8500 addressing flags and operand handling for consistency
* refactor: update H8500 immediate operand syntax to use '#' prefix for consistency
* refactor: update H8500 addressing modes and mnemonics for consistency
* refactor: add new H8500 instructions BNOT, BSET, BSR, and BTST with operand handling
* refactor: update H8500 opcode definitions and add new CLR and CMP instructions
* refactor: add DADD instruction to H8500 opcode definitions and update related tests
* fix: correct memory copy size in h8500_instruction_parse function
* refactor: add DIVXU, EXTS, and EXTU instructions to H8500 opcode definitions and update tests
* refactor: add JMP instruction to H8500 opcode definitions and update tests
* refactor: add JSR instruction to H8500 opcode definitions and update tests
* refactor: add LDC, LDM, and LINK instructions to H8500 opcode definitions and update tests
* Update librz/arch/isa/h8500/h8500.c
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
* Apply suggestion from @Copilot
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
* Apply suggestion from @Copilot
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
* refactor: update H8500 addressing mode and operand flags to use ut64 type
* refactor: update H8500 addressing modes and add MOV instruction test cases
* feat: add MOVFPE, MOVTPE, and MULXU instructions to H8500 opcode and assembly
* feat: add NEG, NOT, and NOP instructions to H8500 opcode and assembly
* feat: enhance H8500 opcode with new instructions and EA flags
* fix: change enum to typedef enum for addressing mode definition
* pjmp
* pjsr | prts
* rot*
* rt*
* scb
* sh*
* sleep | stc | stm
* sub*
* swap
* tas | trapa | trap/vs | tst
* fin disas
* fix header
* add h8500_reg_name function to retrieve register names
* implement H8500 instruction analysis and operand value extraction
* refactor H8500 addressing modes and operand definitions for clarity
* fix msvc 2017 build
* fmt
* fix: update description for H8500 disassembler plugin
* fix: cmd test
* fix: coff h8500 support
* add author and cpus
* fix: test cmd
* feat: add instruction operand string retrieval and new instruction test
* fix: change operand length type from size_t to int in h8500 instruction parsing functions
* feat: add dsub instruction and update operand syntax in h8500 assembly files
* feat: update h8500 opcode descriptions and add new branch instructions
* Fix coff permissions when rz_coff_perms_from_section_flags returns 0
* Fix missing op->size
* refactor: update addressing mode macros and improve operand handling in h8500
* Refactor assembly syntax for H8500 instructions
- Added spaces for better readability in the assembly instruction definitions.
- Updated the formatting of operand lists to include spaces around commas.
- Ensured consistency in the formatting of immediate values and register references.
- Adjusted the assembly test cases to reflect the new formatting style.
* fix: correct permissions for .drectve sections in COFF format
* feat: add initial test cases for h8500 registers and analysis
* fix: add comment to clarify H8300 machine definition in COFF specs
* fix: correct typo in expected output for h8500 analysis
* fix: update data type and constants for H8500 pattern checks
* fix: apply suggestion
* fix: update H8500 instruction encoding and address modes
* fix: add cmp.b and cmp.w instructions for H8500
* fix: refactor H8500 analysis for improved address mode handling
* fix: enhance H8500 analysis for improved operand handling and stack operations
* fix: improve operand handling in H8500 analysis for better instruction processing
* fix: update PJSR instruction format for H8500 and enhance CMP instruction handling
* fix: enhance H8500 function analysis with additional metadata for varfunc and leaffunc
* fix: add documentation and clarify PC-relative mode handling in H8500 instruction parsing
* fix: correct PJMP instruction format to include address dereferencing
* Update librz/arch/isa/h8500/h8500.c
Co-authored-by: Giovanni <561184+wargio@users.noreply.github.com>
---------
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: wargio <deroad@kumo.xn--q9jyb4c>
Co-authored-by: Giovanni <561184+wargio@users.noreply.github.com>
It loads .mdt firmware layout files, searches for the other parts in the same directory and loads them.
It resolves symbols, sections etc automatically, and maps them according to the layout
to the virtual address space.
- The iH command provides details about each firmware part as well.
- Memory maps and segment names are prefixed with the parts file name to make them distinct.
- If a firmware part is an ELF library it loads, and resolves its functions, segments etc.
Due to the design of the ELF binary plugin (code duplication with macros for 32/64bit versions),
this only supports 32bit firmware images for now.
This can relatively easily be fixed, by duplicating this plugin but including the 64bit ELF headers.
This requires more tests though.
* Refactor: improve `rz-bin -L` output
Added `author` + `license` cols
Removed `bin/xtr` col
* Refactor: move `license` column + change table output
moved license column before description
table output for bin/xtr now contains `author` + `license` cols
* Add: author field for `librz/bin/p/*`
author selected on oldest SPDX owner
if same time-period then author is chosen based on git history
* Added build files [Capstone to Zydis]
* x86 Analysis [Capstone to Zydis]
* Changed x86 RzIL [Capstone to Zydis]
* Changed asm and arch files [Capstone to Zydis]
* Compilation, build error and test fixes [Capstone to Zydis]
* Test changes [Capstone to Zydis]
* Remaining changes [Capstone to Zydis]
* Added BE support [Capstone to Zydis]
---------
Co-authored-by: tushar3q34 <tushar3q34@gmail.com>
Implements most of the normal MIPS32 isa from MD00086 Rev 5.04
Breakpoints, syscalls, interrupts, TLB, cache, prefetch and traps are NOP
Does not implement MIPS64, FP, COP2 and HW operations.
* Add xtensa arch capstone plugin
* Remove xtensa-gnu
* fix: `asm.cpu` is not set correctly, when there is no “,” in asm plugin -> cpus
* fix core_disassembly when n_bytes==0
* fix xtensa_analyze_op_esil
* fix xtensa esil pc mod
* fix xtensa esil l32r
* fix xtensa esil call0
* fix xtensa esil extui
* fix xtensa esil store
* fix xtensa stack inc and ret
* keep `asm.cpu` when valid in cb_asmarch
* fix cb_asmarch
* fix max op size
* xtensa: add cpu select
* xtensa: mark PUSH POP
* xtensa: set src dst
* xtensa: set dir
* xtensa: fix stackframe
* Refactor: Use HtSP for storing plugins.
This saves iterations when searching for a plugin of a given name.
It also allows to save plugin configurations and data in hash table,
all addressed by their name. Hence, usage is more streamlined.
* Fix: iterators iterate over pointers of pointers.
* Soften the NULL check.
If arch is passed on from another struct, NULL is an allowed invalid value.
* Fix some leaks
* Fix NULL checks and incorrect inits
* Fix more leaks
* Add warning if plugin with same name was added before and is overwritten.
* Document rz_str_cmp
* Add function to create new list from iterator.
* Sort plugins alphabetically when listed.
* Fix parameter attributes, NULL checks, leaks and single rename.
