This makes all daigrams have their first address at the end of the
diagram and their last address at the start of the diagram.
Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
Each architecture now only needs to describe the bounds of the three
memory regions: the 1:1 mapped physical memory region, the kernel ELF
region (which may or may not overlap the physical memory region) and the
device / kernel page table region.
The physical base address of the 1:1 mapped physcial memory region and
the kernel ELF region must also be specified.
The top of user addressable memory (where in the same virtual address
space as the kernel) is defined by USER_TOP.
The physic memory virtual mapping is described by PPTR_BASE and
PPTR_TOP. The base physical memory address is PADDR_BASE and is the
physical address used to map PPTR_BASE.
Don't use kernelBase when referring to the base of the 1:1 mapped
physical memory window.
The kernel ELF virtual address region is described by KERNEL_ELF_BASE
and extends until the virtual address of the symbol `ki_end` which is
created by the linker. KERNEL_ELF_PADDR_BASE is the base address of
the physical memory region used to map the kernel and is the address to
which KERNEL_ELF_BASE maps.
KERNEL_ELF_BASE and KERNEL_ELF_PADDR_BASE do not need to be aligned to a
page size boundary as they are approriately truncated during boot by the
`map_kernel_window` function.
KDEV_BASE describes the base virtual address of the kernel device region
and the region is assumed to extend to the end of virtual memory.
Note: The offset between PPTR_BASE and PADDR_BASE is used to translate
the virtual address of all untyped objects to physical addresses. This
includes device untyped objects or frame objects where the virtual
address does not fall within the 1:1 mapped physical memory region.
Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.
This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.
Every platform has to implement a standard set of interrupt interfaces
that the kernel uses to interract with a machine's interrupt controller.
Providing a single header file for each of these functions provides a
single location to document their behavior.
Currently on x86 device untypeds are generated by passing the entire
address space minus any parts that are reserved by the kernel or that
are "real" memory (e.g. kernel image, physical RAM).
On ARM and RISC-V, device untypeds were generated at compile-time from
a device tree. This patch moves ARM and RISC-V to use the same approach
as x86, and moves the code from x86 into a common location that's
shared between the three architectures.
Co-Authored-By: Anna Lyons <anna@gh.st>
Reserved IRQ reporting would print on every received reserved IRQ. This
feature is supposed to report spurious interrupts, yet most cases
reserved IRQs are not spurious. We change the printing to only print if
the reserved IRQ was unhandled. The intention is to allow more app
configurations to leave this feature enabled in development builds.
Preemption can be via the timer interrupt. In this case we need to
update the timestamp so we can reprogram the timer for the next timeout
and guarantee it is in the future, otherwise we will end up setting a
timeout in the past.
The DTS compilation was arm platforms only. Moving it to the top level
config file, making it available to RISCV platforms. The generated files
are almost identical with minor differences. A new argument(--arch) is
added to the hardware_gen.py for the differences.
Prior to this change, the boot process would dynamically allocate
memory for root server objects based on the order of initialisation.
Allocation was a best-fit algorithm.
This change preallocates all memory for root server objects to an
aligned untyped just after the user image. By allocating the objects in
order of size, allocation is greatly simplified and the ability to
reproduce the allocation offline based on the kernel and user image
sizes is increased.
We add support for seL4_IRQControlGet and seL4_IRQControlGetTrigger. If
a platform doesn't support setting the trigger, then
seL4_IRQControlGetTrigger will return an error. If the platform doesn't
have a PLIC driver, then it won't have any IRQs that can be requested.
Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
Previously we only handled IRQs generated by the BBL running in machine
mode via changes to supervisor interrupt pending (SIP) bits. Now that we
need to support shared global interrupts through the PLIC we need to
modify the way interrupts are processed.
We additionally remove many DONT_TRANSLATE annotations on functions that
the CParser is able to parse.
Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
We assume the PLIC is currently the only global interrupt controller
that RISC-V platforms are going to use. Each platform may have a
different programmers model for interracting with the hardware
controller. We provide a common interface for PLIC drivers to implement
that the kernel will use to manage IRQs.
Also authored by: Siwei Zhuang <siwei.zhuang@data61.csiro.au>
- Create device untypeds for platform devices that can be passed to user
space.
- Create kernel device mapping for devices required by the kernel.
Note that the current kernel device mapping is simply a 1GiB of page
physical memory as that contains all devices for all RISC-V platforms
that are currently supported.
For now we keep the RISC-V platforms under the spike kernel platform
name. Splitting the different platform definitions into different header
files will help maintainability as we add different device layouts and
kernel device drivers.
PPTR_USER_TOP represents the first inaccessible user address which is
usually ((2^(38-12))-1)*0x1000 on SV39. This corresponds to the first
address of the last page in the lower half of the top level page table.
Add a comment and diagram explaining the current structure of the SV39
kernel address space. The top half of the virtual address space is
reserved for the kernel and consists of the Kernel window of all
accessible physical memory, the kernel ELF mapping and the Kernel device
mapping region.
There is a 1GiB region reserved at the top of the Kernel virtual address
space to map devices used by the kernel into. The start of this range is
referred to by PPTR_KDEV. This also represents the end of the Kernel ELF
window mapping.
Verification requires the KERNEL_BASE to be 1GB aligned at the start of
the kernel elf window. It was also the location where the kernel elf was
mapped. As we have to include SBI memory in the kernel elf window,
the KERNEL_ELF_BASE is introduced for the real kernel elf mapping.
Keeping KERNEL_BASE unchanged.
init_freemem sets up available regions of memory for the hardware that
seL4 is booting on. Previously this function was duplicated across
architectures, with minor duplication.
This change provides a top-level init_freemem suitable for all
architectures.
- arm/riscv: change get_avail_p_reg to return whole p_reg array
- update all architectures to use new init_freemem.
- wrap init_freemem calls with arch_init_freemem for each arch, where
arch_init_freemem sets up the available and reserved regions of memory
which are passed to init_freemem.
The memory used for the irq cnode is never available to the user. As a
result this memory can be allocated statically, simplifying the
bootcode.
- remove allocation of irq cnode
- add static init
- generate irq cnode size from cmake for arm
- add static constants for riscv, x86 as there is no variability at the
moment.
This allows for arm headers to be generated for an arm platform
in include/plat/default that specifies the following:
- maxIRQ
- TIMER_CLOCK_HZ
- the timer header to use
- the interrupt controller header to use
This commit updates the ia32 build to pass the c-parser.
- replaces ++i with i++
- use void in functions with no parameters
- add a missing typecast
- remove a void cast of an unused variable
It does not provide any verification guarantees about ia32 code.
The SBI memory was mapped outside the kernel window. This would trigger
an instruction access fault on some hardware, when the bootloader has set
up PMP to protect the SBI memory. Instead of protecting a particular memory
region, the PMP locks the entire page table entry that covers the region.
The PADDR_LOAD and kernel base are adjusted to have the SBI memory
included in the kernel window. So that the SBI memory can be mapped as
part of the kernel image to a separate page table entry. This also
avoids the kernel to allocate untyped memory from the SBI region.
These files can be included normally using libsel4 include paths. This
removes situations where the same file is available under different
include paths due to symlinking into different directory structures.
The C parser produces abbreviations for local variables that depend on
the variable type and the order they appear in the source.
The signature for `get_avail_p_reg` on RISCV has a different type for
`i` than every other function, which causes issues when `hardware.h` is
included early in `kernel_all.c_pp`. Changing the type to `word_t`
avoids these issues.
