Commit graph

330 commits

Author SHA1 Message Date
Anna Lyons
d0930f67de style: consistently attach return type
Add attach-return-type to astyle
2019-03-19 14:05:36 +11:00
Anna Lyons
761006e03b style: consistently align pointer with name
Run astyle with align-pointer=name
2019-03-19 14:04:54 +11:00
Anna Lyons
3d10ef0c4d style: correct parenthesis padding
Use astyle's unpad-paren to unpad all parentheses that are not included
by pad-header, pad-oper, and pad-comma.
2019-03-19 14:02:59 +11:00
Siwei Zhuang
3914931b32 RISCV: Remove hartid and DTB parsing from the boot code. 2019-03-19 13:39:36 +11:00
Sylvain Gauthier
63ed19c9b7 handleReservedIRQ now implemented on arch level except for pc99 2019-03-14 15:23:54 +11:00
Sylvain Gauthier
330cbfbdad Made declaration of handleReservedIRQ optional, refactored consequently 2019-03-14 15:23:21 +11:00
Simon Shields
5cd3b7e317 zynqmp: Remove devices.h
These values are now autogenerated.
2019-02-15 14:05:06 +11:00
Kent McLeod
89dd2603b6 arm: Remove empty level2 cache code 2019-02-15 12:39:09 +11:00
Kent McLeod
7f34e19a43 Remove empty hardware.bf definitions
These have no effect when there aren't any definitions.
2019-02-13 14:21:04 +11:00
Simon Shields
0fac956e9f ARM platforms: use auto-generated kernel_devices
Note that the auto-generated kernel_devices will differ slightly from
the ones present in the kernel until now. When devices have
registers that aren't page-aligned we now always set the appropriate
PPTR to be the start address of the device, while previously the PPTR
was sometimes page-aligned.

Specifically, this change to PPTRs affects:
- bcm2837 intc
- bcm2837 uart
- allwinnerA20 timer
2019-02-05 14:47:38 +11:00
Simon Shields
3989d95473 arm: use UART_PPTR for all uarts 2019-02-05 14:47:38 +11:00
Simon Shields
dcc8f7ec39 arm: use auto-generated interrupt numbers
This removes the big tables of interrupt numbers from each platform.
2019-01-16 14:46:08 +11:00
Simon Shields
fc4447708a arm: use DTS to generate memory region lists
This changes all ARM platforms over to using the device tree found in
the kernel to generate memory region information.
2019-01-16 14:45:56 +11:00
Simon Shields
4d2bd90c84 tx2: adjust PHYS_BASE to match generated one
Move PHYS_BASE 16MiB into RAM to match the /memreserve/ in the DTS.
2019-01-16 14:37:13 +11:00
Simon Shields
86da489f6b exynos5: adjust PHYS_BASE to match generated one
Adjust PHYS_BASE to the start of RAM to match the DTS.
2019-01-16 14:36:19 +11:00
Simon Shields
d6b1dcf962 allwinnerA20: remove irqNumbers enum 2019-01-15 11:16:04 +11:00
Kofi Doku Atuah
91969a9038 AArch64: Benchmark log: Add convenience pointer to PD entry
* Also document the reason why the particular address for KS_LOG_PPTR was chosen.

This patch adds a pointer to the PD entry that sets the benchmark log frame.
2019-01-15 09:05:15 +11:00
Simon Shields
468d1c5505 am335x: use KERNEL_TIMER_IRQ for timer IRQ number 2019-01-08 13:07:36 +11:00
Simon Shields
73874a75df omap3: use KERNEL_TIMER_IRQ for timer IRQ number 2019-01-08 13:07:36 +11:00
Curtis Millar
da3b028650 Add system timer device untyped for BCM2837 (RPi3) 2019-01-03 12:41:43 +11:00
Curtis Millar
2fd77252e3 Reflow style of physical device frame list. 2019-01-03 12:41:43 +11:00
Anna Lyons
5fe6d0bcef riscv/spike: fix seL4_UserTop for riscv
Use correct values and document them.
2018-12-20 12:27:23 +11:00
Anna Lyons
4bc6b76f5f Remove empty plat_mode/machine header files 2018-12-12 16:24:31 +11:00
Anna Lyons
2a0d682ff2 Remove MAX_IRQ
MAX_IRQ was used on several platforms. Remote it. This is a layer of indirection which adds no value.
2018-12-12 16:24:31 +11:00
Anna Lyons
403f5dace7 Remove N_INTERRUPTS constant
The N_INTERRUPTS constant is never used. maxIRQ tracks this value.
2018-12-12 16:24:31 +11:00
Anna Lyons
e5bb674594 Calculate IRQ_CNODE_BITS from maxIRQ
IRQ_CNODE_BITS is determined by the maxIRQ on the platform. Calculate
this value from maxIRQ instead of hardcoding for each platform.
2018-12-12 16:24:31 +11:00
Anna Lyons
76faadc923 Add seL4_UserTop and move kernelBase to the arch level
- seL4_UserTop is a new constant which represents the top of virtual
memory available to user level
- this commit also rationalises several constants (USER_TOP, kernelBase)
and moves them to the arch level, such that ports only need to define
seL4_UserTop.
2018-12-12 16:24:31 +11:00
Kofi Doku Atuah
fbec286d97 AArch64: Comment HYP and EL1 vaddrspace layouts
Also document the specific addresses for TX1 and TX2.
2018-12-11 18:27:32 +11:00
Kofi Doku Atuah
e46445c557 TX2: AArch64: Hyp: Use the correct conditional timer IRQ 2018-12-11 18:27:32 +11:00
Kofi Doku Atuah
479cd82dbe TX2: AArch64 Hyp: Add GICH controller paddr 2018-12-11 18:27:32 +11:00
Kofi Doku Atuah
0b933ea7a3 TX2: AArch64 HYP: Set EL2 mode addresses 2018-12-11 18:27:32 +11:00
Edward Pierzchalski
2d075c2760 riscv: remove spurious MODIFIES specs.
Until these functions have non-empty definitions, the C parser will spit
out warnings about ignoring the MODIFIES spec.
2018-12-06 15:04:41 +11:00
Peter Chubb
896e864431 TX2: Add initial TX2 support
See CHANGES and https://docs.sel4.systems/Hardware/ for more information
2018-11-07 11:52:51 +11:00
Axel Heider
8cf34ab395 add missing include for config.h
These files contain conditional parts which depends on CONFIG_PLAT_xxx being set, thus they must include config.h.
2018-09-24 11:03:14 +02:00
Axel Heider
924d1c2639 zynqmp: add Ultra96 platform
Add Ultra96 platform, which is based on the zynqmp SoC
2018-09-14 16:16:23 +02:00
Adam Felizzi
72e675f1da Kbuild: Removed Kbuild
Removed all Kbuild/Kconfig/Makefiles from the kernel as we migrate
to a CMake only build system. Kbuild is no longer supported.
2018-08-10 10:38:53 +10:00
Adrian Danis
3eefc3e7c2 riscv: Make room for devices in rv32
Leaves the last entry in the top level page table free so that it can be used for mapping
devices in the future. This moves the kernel image down to the second last entry in the
top level page table. Leaving the last entry in the top level page table also matches the
rv64 design.
2018-08-09 12:36:28 +10:00
Jesse Millwood
3db47a881e riscv: PADDR_LOAD changed when running on the rocket-chip
This change is required because the zedboard rocket-chip only has
256MiB of memory. Therefore the load address needs to be lowered
to fit in the available range.

This change will also require the kernel to be mapped with 2MiB
granularity so everything is properly page aligned.

Change-Id: I75ddec0be1bb2fd05d0a947ea19bce46e2cd9f96
2018-08-09 10:43:42 +10:00
Sebastian Holzapfel
5f1d63becf rpi3/aarch64: update linker script & relocate PHYS_BASE
rpi3 documentation states RAM *should* be mapped from 0x00000000 onwards,
but we omit the start of physical memory as it caused early boot issues
on access. Instead use u-boot's default kernel load address as PHYS_BASE.
2018-06-04 13:46:19 +10:00
Sebastian Holzapfel
26b66ba92c rpi3: fix PADDR_OFFSET nit 2018-06-04 13:45:44 +10:00
Sebastian Holzapfel
6033fad28a rpi3/aarch64: add aarch64 memory map 2018-06-04 13:44:08 +10:00
Nathan Studer
b15d1476d5 Support a PADDR base other than 0
Several of the mapping calculations rollover when dealing with 32-bits due to the location
of memory on spike, the kernel/user window addresses, and the kernel load address.

Adjust the kernel window so that it covers the typical location of memory on
spike.
2018-05-10 12:44:19 -04:00
Anna Lyons
d3feb06cdd riscv: fix licenses
- add files from elsewhere to the license ignore
- s/D61_BSD/DATA61_BSD
2018-04-18 10:52:02 +10:00
Anna Lyons
76c61025ac riscv: remove dev_pregs
We don't have any devices currently, and in future they will be
discovered, not statically specified.
2018-04-18 10:10:14 +10:00
Adrian Danis
6938c98adf riscv: Fill physical memory regions from FDT
Removes the hardcoded physical memory region from the spike platform and fills it from
FDT parsing instead.
2018-04-18 10:10:14 +10:00
Adrian Danis
ee37eebcae riscv: Cleanup FDT code
Rewrites the FDT code to remove all the disallowed function pointers have attempt to perform
the equivalent functionality of query_mem in place in the main parser. With the callback
system gone all the rest of the unused FDT code is deleted as it doesn't make sense.
2018-04-18 10:10:14 +10:00
Adrian Danis
22b050c95d riscv: Redesign kernel window
Restructures the kernel window so that instead of being a single contiguous region with
a single offset to physical memory, it is two such regions. This allows us to use the
larger of the two windows as a window into physical memory, and the second smaller window
as a place to run the kernel image from. Having this additional window allows us to
link the kernel for different physical addresses without needing to change its virtual
address, or change the layout of the kernel window.
There are other ways to achieve this, but this is one of the simplest and matches how
x86-64 implements its kernel window.
2018-04-18 10:10:14 +10:00
Anna Lyons
0764d2ac7d riscv: build on 32 bit 2018-04-18 10:10:14 +10:00
Adrian Danis
c825805658 riscv: Remove empty unused header 2018-04-18 10:10:14 +10:00
Adrian Danis
300c5a7ede riscv: Rationalize IO definitions
This removes some duplicate (and incorrect) definitions that already exist in common
code and removes some unimplemented functions that are not used due to the current
absence of capDL dump support
2018-04-18 10:10:14 +10:00
Hesham Almatary
6af207a078 RISC-V: Port FDT from riscv-pk (priv-1.10) 2018-04-18 10:10:14 +10:00
Adrian Danis
459eb10d66 riscv: Remove dead code
These definitions match no existing kernel interface or abstraction and being removed
2018-04-18 10:10:14 +10:00
Adrian Danis
aafa594258 RISCV: Place TODOs in the source 2018-04-18 10:10:14 +10:00
Hesham Almatary
83ba084713 [SELFOUR-1156] RISC-V Port
Experimental release that supports both RV32 and RV64
2018-04-18 10:10:14 +10:00
Yanyan Shen
b95eb21782 armv8/tx1: Expose more devices to user mode 2018-04-03 10:34:01 +10:00
Yanyan Shen
fa0d3823e3 armv8/tx1: Fix a typo: Kb->KB 2018-04-03 10:34:01 +10:00
Yanyan Shen
a5a118458c armv8/tx1: Handle VGIC_MAINTENANCE interrupts 2018-04-03 10:34:01 +10:00
Anna Lyons
f6ff7806dd define KERNEL_PMU_IRQ for TX1, HIKEY 2018-03-22 13:12:03 +11:00
Yanyan Shen
396cfaac0e armv8/tx1: Map GIC VCPU control interface for EL2. 2018-03-05 16:05:48 +11:00
Yanyan Shen
c1bf4fe432 armv8/tx1: Introduce KDEV_PPTR.
The KDEV_PPTR is defined for EL1 and EL2 differently as the
base for kernel-device virtual addresses.
2018-03-05 15:58:37 +11:00
Yanyan Shen
28014895dd armv8/tx1: Define kernelBase and USER_TOP for EL2. 2018-03-05 15:42:36 +11:00
Yanyan Shen
151506c7bb armv8/tx1: Increase physical memory size for TX1. 2018-03-05 15:35:03 +11:00
Yanyan Shen
5d3154da80 armv8/tx1: Fix a typo
Change GIC_CONTROLLER0_PADDR to GIC_CONTROLLER_PADDR
2018-03-05 15:30:11 +11:00
Yanyan Shen
2337827e3a arm/tx1: Add device physical addresses for TX1. 2018-03-05 15:09:46 +11:00
Yanyan Shen
7ce75bb2ae arm/tx1: Define the IRQs used in EL2. 2018-02-28 10:54:18 +11:00
Hesham Almatary
4812ddf440 SELFOUR-711: Add Eth/CPSW IO addresses to am335x platform 2018-02-13 15:00:28 +11:00
Adrian Danis
4857dcb000 x86: Separate header for TLB bitmap definitions
Having a separate header allows for them to be included into the platform hardware
definition without causing a circular include
2018-01-16 14:51:26 +11:00
Adrian Danis
b851560cf7 x64: Restrict user to non sign extended vaddr
This simplifies the kernel preventing the need to validate that addresses are canonical
on the return from syscalls and interrupts.
2018-01-16 11:33:29 +11:00
Adrian Danis
c8eb525782 pc99: Make hardware.h usable from assembly
Rearranges hardware.h and makes use of the UL_CONST macro so that the header can be
included into assmebly files for its definitions
2018-01-09 14:13:41 +11:00
Adrian Danis
9f9578a7ae aarch64: Restrict USER_TOP to virtual addresses without high bits
Restricting virtual addresses to essentially be only addresses without bit 47 set
allows us to not need to check that an address passed in by the user is canonical
or not. Any address that is in danger of not being canonical (has bit 47 set but
not bits 48 to 63) will all by higher than USER_TOP and will not be permitted.
2017-12-20 16:11:06 +11:00
Alexander Boettcher
a4a52c5dcb pc99: Explicitly declare sizes for different versions of ACPI RSDP 2017-11-28 16:25:07 +11:00
Bamboo
a32264bfb5 [STYLE_FIX] 2017-11-28 00:02:37 +00:00
Anna Lyons
cddc4e6ef5 Inline resetTimer for all platforms
- for arm generic timer platforms, we remove resetTimer ->
resetGenericTimer indirection and simply include generic_timer.h
- this reduces boiler plate for platforms that share timer drivers, as
  they simply include the one header
- there is far more timer code in the RT kernel, which motivates this
change
2017-11-28 10:21:46 +11:00
Anna Lyons
31b8c158ba Trivial: add missing guards 2017-11-28 10:21:46 +11:00
Anna Lyons
7fd2783653 Refactor mct.c into mct.h and hardware.c
This prepares for inlinining the generic timer in header files, which will reduce the
redundancy for all platforms that use it.

Since mct.c shared code with the generic timer, both could not define a
resetTimer function. This commit splits the logic and definitions used
by exynos4 and exynos4* into common definitions in mct.h, with the
unique code for both in hardware.c
2017-11-28 10:21:46 +11:00
Anna Lyons
c89b9828db Make TIMER_CLOCK_HZ available in timer.h for ARM
The RT kernel needs this value accessible to common functions.
2017-11-28 10:21:46 +11:00
Anna Lyons
1a408880f1 Add a timer.h for all ARM platforms. 2017-11-28 10:21:46 +11:00
Joel Beeren
092042f7c5 x64: add MODIFIES statements for extern functions
The CParser can't deduce modifies rules for functions without
definitions (like in8, out8 et al and interrupt handler functions).
This adds explicit modifies rules for these functions.
2017-11-09 12:18:31 +11:00
Adrian Danis
e8625c6d81 pc99: Provide public function for validating an RSDP
RSDP validation was previously done directly in acpi_init. This splits the validation
into a seperate, publicly useable, function. The intention is for this to be used in
boot scenarios where an RSDP is given and does not need to be searched for.
2017-10-06 10:08:46 +11:00
Adrian Danis
ee380609c6 x86: Copy RSDP table in acpi_init instead of returning physical address of rsdt
The full RSDP is useful beyond just extracting the RSDT address out of it. In particular
this prepares us for being able to pass a copy of the RSDP to the rootserver.

The previous function signature might lead a user to believe that they were getting a
pointer to a useable acpi_rsdt_t structure. This was in fact not the case and was
actually returning the physical address, that may or may not be mapped in, of the rsdt
table. All of the other acpi *_scan functions would therefore immediately map in the physical
rsdt pointer they were given.

This commit changes acpi_init to return a boolean indicating whether it found a valid
rsdp, and then fills in a copy of the rsdp data. The copy is necessary as the rsdp
data may be at a temporary mapping.

As a result of changing acpi_init the boot code and state is changed to have a acpi_rsdt_t
instance that can be filled out.
2017-10-06 10:08:40 +11:00
Bamboo
3b84ab41e0 [STYLE_FIX] 2017-10-03 01:18:48 +00:00
Adrian Danis
383a6d959f Merge branch zcu102-7.0.0 into master 2017-10-03 12:16:08 +11:00
Robbie VanVossen
4ba89d4aa0 Added 64-bit support for the zynqmp.
Split up the bit specific code into new folders and added 64-bit
support. Also, changed the device register sizes to be based off of
PAGE_BITS instead of a hardcoded number.

TIMER_CLOCK_HZ is set to the default clock rate from the ATF,
which is the same for both AARCH32 and AARCH64.It may require changes
to the FSBL to work correctly.
2017-09-27 12:59:07 -04:00
Robbie VanVossen
02ca6a80a4 Added 32-bit support for the zynqmp.
The Zynq UltraScale+ MPSoC (PLAT zynqmp) is a Multi-Processor SOC
made by Xilinx that has a quad-core Cortex-A53, a dual-core Cortex-R5
and an FPGA.

This adds 32-bit, single-core support on the the Cortex-A53 cluster.
2017-09-27 12:58:49 -04:00
Adrian Danis
95b505bee2 pc99: Make irq_t a uint8_t type instead of an enum type
This renames the previous irq_t enum into a platform_irq_t enum and provides irq_t
as a 'well defined' uint8_t typedef. Having irq_t be an integer type, and not an enum,
is necessary for consistency with verification. As part of explicitly defining irq_t
as an unsigned integer type the definition of irqInvalid is changed to prevent sign
extension leading to unexpected invalid comparisons.
2017-09-26 16:57:10 +10:00
Adrian Danis
2bf586fe3d x86: Correct return type of servicePendingIRQ
This function returns an interrupt_t, and its call sites expect an interrupt_t,
despite the types being written as irq_t.

Closes #66
2017-08-29 10:56:43 +10:00
Adrian Danis
a9e1f51713 SELFOUR-1062: Hide all IOMMU related code behind #ifdef guards
The IOMMU implementation is not going to be verified at the moment, and so the code for
it needs to be hidden from verification, which we do by #ifdef'ing it out if the IOMMU
is not enabled. As a result the IOMMU configuration depends on a non verification target
2017-08-21 16:44:58 +10:00
Adrian Danis
8c8b53a5f7 pc99: Define PCI helpers in a pci header instead of iospace header
These helpers are generic PCI and are used outside of the iospace code
2017-08-21 16:44:58 +10:00
Hesham Almatary
57fa0e0f85 Share linker.h between architectures 2017-08-10 08:38:36 +10:00
Hesham Almatary
ee28936d48 SMP: Introduce ENABLE_SMP_SUPPORT
- Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check
2017-06-29 16:23:39 +10:00
Anna Lyons
40c61e5c18 Fix licenses (the rest) 2017-06-22 15:29:12 +10:00
Jonas Claeson
d8c31a8583 Removed unnecessary comparison in updateIRQState
./kernel/include/plat/pc99/plat/machine/interrupt.h:115:14:
error: comparison of unsigned expression >= 0
      is always true [-Werror,-Wtautological-compare]
    if(!(irq >= 0 && irq <= maxIRQ)) _assert_fail(...
         ~~~ ^  ~
2017-06-13 16:50:43 +02:00
Yanyan Shen
c6900c98e7 arm/imx7: add/correct dev mem/int; generic timer
Add more device memory regions and interrupts.
Merged Anna's generic timer impl.
2017-06-09 10:48:57 +10:00
Adrian Danis
1f2f6b98bb Use CONFIG_ variables instead of configuration definitions 2017-05-29 17:04:47 +10:00
Adrian Danis
551e73f22f Check for configuration variables being 'defined' instead of 'true'
This is to conform with existing style of checking configuration options
2017-05-03 10:35:44 +10:00
Adrian Danis
4e3839e315 Move standalone autoconf.h files out of include directories
When performing non standalone builds a separate autoconf.h file is generated and defines
the configuration of the kernel. Currently the directory with that file as well as the
kernels include/plat/${PLAT} directory are both listed as include directories to the
compiler. Due to the directory with the generated autoconf.h being earlier in the -I
list the generated autoconf.h will be used in preference to the standalone autoconf.h.

Relying on the order of -I directives is too unstable and so this commit moves the
autoconf.h files to a dedicated configs directory, which is only added as a -I
directive if a standalone build is being performed.
2017-04-10 11:16:57 +10:00
Rafal Kolanski
7680bab494 tk1: disable SMMU in autoconf.h
This is overwritten by KConfig but used on verified platform where the
SMMU is likely to come much later.
2017-04-05 09:50:52 +10:00
Rafal Kolanski
9b17e8afca tk1: maxIRQ off-by-one w.r.t. N_INTERRUPTS 2017-04-04 15:59:40 +10:00
Rafal Kolanski
9098528719 tk1: set CONFIG_NUM_DOMAINS=16 for verified kernel 2017-04-04 11:55:07 +10:00
Bamboo
9601f0fdfe [STYLE_FIX] 2017-03-09 02:36:15 +00:00