It loads .mdt firmware layout files, searches for the other parts in the same directory and loads them.
It resolves symbols, sections etc automatically, and maps them according to the layout
to the virtual address space.
- The iH command provides details about each firmware part as well.
- Memory maps and segment names are prefixed with the parts file name to make them distinct.
- If a firmware part is an ELF library it loads, and resolves its functions, segments etc.
Due to the design of the ELF binary plugin (code duplication with macros for 32/64bit versions),
this only supports 32bit firmware images for now.
This can relatively easily be fixed, by duplicating this plugin but including the 64bit ELF headers.
This requires more tests though.
* Refactor: improve `rz-bin -L` output
Added `author` + `license` cols
Removed `bin/xtr` col
* Refactor: move `license` column + change table output
moved license column before description
table output for bin/xtr now contains `author` + `license` cols
* Add: author field for `librz/bin/p/*`
author selected on oldest SPDX owner
if same time-period then author is chosen based on git history
* Added build files [Capstone to Zydis]
* x86 Analysis [Capstone to Zydis]
* Changed x86 RzIL [Capstone to Zydis]
* Changed asm and arch files [Capstone to Zydis]
* Compilation, build error and test fixes [Capstone to Zydis]
* Test changes [Capstone to Zydis]
* Remaining changes [Capstone to Zydis]
* Added BE support [Capstone to Zydis]
---------
Co-authored-by: tushar3q34 <tushar3q34@gmail.com>
Implements most of the normal MIPS32 isa from MD00086 Rev 5.04
Breakpoints, syscalls, interrupts, TLB, cache, prefetch and traps are NOP
Does not implement MIPS64, FP, COP2 and HW operations.
* Add xtensa arch capstone plugin
* Remove xtensa-gnu
* fix: `asm.cpu` is not set correctly, when there is no “,” in asm plugin -> cpus
* fix core_disassembly when n_bytes==0
* fix xtensa_analyze_op_esil
* fix xtensa esil pc mod
* fix xtensa esil l32r
* fix xtensa esil call0
* fix xtensa esil extui
* fix xtensa esil store
* fix xtensa stack inc and ret
* keep `asm.cpu` when valid in cb_asmarch
* fix cb_asmarch
* fix max op size
* xtensa: add cpu select
* xtensa: mark PUSH POP
* xtensa: set src dst
* xtensa: set dir
* xtensa: fix stackframe
* Refactor: Use HtSP for storing plugins.
This saves iterations when searching for a plugin of a given name.
It also allows to save plugin configurations and data in hash table,
all addressed by their name. Hence, usage is more streamlined.
* Fix: iterators iterate over pointers of pointers.
* Soften the NULL check.
If arch is passed on from another struct, NULL is an allowed invalid value.
* Fix some leaks
* Fix NULL checks and incorrect inits
* Fix more leaks
* Add warning if plugin with same name was added before and is overwritten.
* Document rz_str_cmp
* Add function to create new list from iterator.
* Sort plugins alphabetically when listed.
* Fix parameter attributes, NULL checks, leaks and single rename.
Uplift Hexagon architecture to RzIL
The general structure is, that every (sub-)instruction has a getter for it's RzIL code.
Calling the getter will return the RzIL operation.
If RzIL for an instruction is requested, the plugin makes a decision. Because Hexagon only executes whole instruction packets. If the instruction is not the last instruction in a packet, it will simply return `EMPTY()`. If the RzIL for the last instruction in a packet is requested, it will get the RzIL operations for all instructions in the packet, shuffles them into the correct execution order (according to some rules) and returns the complete operation for the packet.
The RzIL code was entirely generated with the [rzil-compiler](https://github.com/Rot127/rzil-compiler/), using the semantic definition of the [QEMU Hexagon module](https://github.com/qemu/qemu/tree/master/target/hexagon).
Currently successful compile instructions (and tested):
```
[*] 1581/1733 standard instructions compiled.
[*] 431/643 HVX instructions compiled.
[*] In total: 2012/2376 instructions compiled.
```
It was tested with:
- (Semantic tests) `rz-tracetest` against the execution trace of the QEMU Hexagon test binaries.
- (Bug free and semi-semtantic test) Adding tests which simply execute the test binaries to ensure leak and segfault free execution. Also it is executed until a certain instruction is reached (end of `main` or `loc.pass` symbol), partially testing it executes correctly.
For the uplifting several changes and modernization had to be made:
- Enhance consistency of decoding
- Allow to disassemble an instruction without copying the result. This is used if the given buffer of instruction bytes is larger than one instruction width. In this case, as many instructions as the buffer can hold are disassembled and buffered for later.
- Generally enhance buffering of instructions.
- Allow to mark a packet as valid before it is completely decoded (in case we know it must be valid, e.g. if it is a jump target of a valid packet).
- Fix (hopefully) all memory leaks of the Hexagon plugin.
- Changes to register getters, because RzIL needs finer control to translate alias or explicit register names to their real register.
- Getter for register name is now done by table, so for future distinction between DSP version we can just select another table.
- Translation functions from register alias or explicit name to their real register.
- Each operand contains now it's variable ID (e.g. `d` for register `Rd`) as in the ISA (for mapping in the RzIL code).
- Ease debugging by tracking in more precision, if an instruction is added to a stale, active or new packet.
- Add registers `C20` - `C29` (not yet present in LLVM)
- Some renaming to make the code more readable.
* Basic framework of rx implemented
* Add match and parse flow
* Add part of description for RxV1 instruction set
* Add datasheet for rxv1
* Implement stringify op for rx
* Add missing TST instruction in datasheet
* Test to div instruction and fix bugs
* Test known rxv1 instruction set
* Fix bugs in rx disasm plugin and add SPDX
* Add rz_analysis for renesas rx
* Fix rz_analysis bug for renesas rx
* Add rz_asm test and fix bug in datasheet
* Add analysis test and fix bugs for renesas rx
Entire files are now avoided to be built by checking in meson rather
than using #if DEBUGGER. This now also includes bsd_debug.c, which
is currently slightly broken on OpenBSD/sparc64 and caused compile
errors even with -Ddebugger=false.
