The condition element currently exists parallel
to the condition attribute. The condition attribute
should be removed in a subsequent patch.
Signed-off-by: matt rice <ratmice@gmail.com>
This patch restricts mixed-content elements from ANY
to the various leaf nodes which are used.
This is intended to allow for easier parsing in languages with
no recursive datatypes like rust.
Since they no longer have to handle things like
'<description> text
<description>more text</description>
<description>'
which the dtd allowed for, but never used.
tested with:
for i in {libsel4/arch_include/*/interfaces/,\
libsel4/include/interfaces/,\
libsel4/sel4_arch_include/*/interfaces}/*.xml;
do
xmllint --noout --dtdvalid libsel4/tools/sel4_idl.dtd $i;
done
Signed-off-by: matt rice <ratmice@gmail.com>
This adds an alternative script for syscall_stub_gen.py
syscall_stub_gen_rs.py was initially derived from Robigalia project
which can be found here: https://gitlab.com/robigalia/sel4-sys
However, this is no longer compatible.
The script is intended to be used with a proper sel4-sys crate
in order to allow Rust applications to interface with the seL4 API.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This reverts a small part of 1596aa5857 which unexpectedly broke the
binary verification frontend, because the verification tool chain
forces the enum to `int` instead of `long`.
See also seL4 issue #738 -- when that issue is solved, we may be
able to go back to the more specific type.
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
* use enum for SEL4_BOOTINFO_HEADER_xxx
Also add more comments and use seL4_BootInfoID in seL4_BootInfoHeader.
Signed-off-by: Axel Heider <axelheider@gmx.de>
Commit 8035f1a7c4 removed "-fno-integrated-as" for llvm, which on more
recent versions (clang-11) means that we now need `#` instead of `$`
for immediate values.
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
Remove a userError that is present on mainline kernel but not on MCS.
seL4_ReplyRecv is often used in a loop to create an event handler. When
first entering this loop, or when handling signals from notifications,
there won't already be a pending caller blocked on the reply object. In
this case the kernel doesn't perform a reply transfer and continues with
the receive operation. This is a common operation and shouldn't result
in a userError being printed by the kernel each time the reply phase
ends up as a no-op.
Signed-off-by: Kent McLeod <kent@kry10.com>
Align the API wrapper guards with the kernel syscall implementation,
the function is available if CONFIG_ENABLE_SMP_SUPPORT is set instead
of depending on CONFIG_MAX_NUM_NODES.
Signed-off-by: Axel Heider <axelheider@gmx.de>
32-bit architectures have to share a small 4GiB address space between
privileged and non-privileged modes. Picking the address to split the
address space at affects how much virtual memory userlevel can use, and
how much physical memory the kernel can turn into untypeds. This is
something that should be configurable policy as different divisions make
sense for different applications. For now we only add the config
option to qemu-arm-virt to try it out before potentially adding it to
all 32-bit platforms.
Signed-off-by: Kent McLeod <kent@kry10.com>
Mutate cannot be used to badge endpoints (many years ago, before the
first public release, this was possible, but was removed).
Also explain why Mutate is not always replaceable with Mint+Delete.
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
Add error conditions for the lazy bind of SchedContexts to
notifications or TCBs (introduced in e18e32e28e).
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
- seL4_FailedLookup in X86IOPageTableMap
- seL4_FailedLookup in ARM page invalidation operations
- seL4_FailedLookup in ARMASIDPoolAssign
Signed-off-by: Jimmy Brush <code@jimmah.com>
- KernelGlobalsFrame caused the definition of seL4_GlobalsFrame which
was a reservation at the top of the user address space on ARMv6
platforms.
- KernelDangerousCodeInjectionOnUndefInstr was used to implement calling
user code in kernel mode won ARMv6.
Signed-off-by: Kent McLeod <kent@kry10.com>
The platform was the original verification target of seL4 over 10 years
ago and by now there doesn't appear to be any ways to obtain new
hardware.
Currently, the KZM platform is the only ARMv6 platform and supporting it
requires a few work-arounds for emulating mechanisms that newer hardware
supports. Removing this platform also implies removing armv6 support
soon.
Signed-off-by: Kent McLeod <kent@kry10.com>
In x86, EPT and normal mappings have different cache attributes. This
commit adds an enum for the EPT attributes.
Signed-off-by: Chris Guikema <chris.guikema@dornerworks.com>
Define CONFIG_KERNEL_LOG_BUFFER in the same way as all other kernel
config options so that it is present in autoconf.h
Signed-off-by: Kent McLeod <kent@kry10.com>
autoconf.h is expected to contain all defined config options for an seL4
build configuration. Having these redefinitions were leftover from when
the verification build system didn't produce an autoconf.h file and set
the config separately. Its more likely that these defaults would
incorrectly hide an include path misconfiguration and produce settings
that are inconsistent with the kernel's configuration.
Signed-off-by: Kent McLeod <kent@kry10.com>
TQ Group produces a system-on-module family called TQMa8Xx.
The user manual for this SoM is available here:
https://www.tq-group.com/filedownloads/files/products/embedded/manuals/arm/embedded-modul/TQ-Socket/TQMa8Xx/TQMa8Xx.UM.0104.pdf
This SoM comes in a number of different configurations.
The specific NXP SoC used, and the amount of memory are both
configurable.
The TQMa8XQP is the part number for the TQMa8Xx family configured with
the i.MX 8QuadXPlus SoC.
The datasheet for the SoC is available here:
https://www.nxp.com/docs/en/data-sheet/IMX8QXPAEC.pdf
In addition to the SoC being configurable the amount of SDRAM
on the SoM is also configurable.
The support provided in this PR is specifically for the TQMa8XQP
configured for 1GiB of memory. Note: Actual usable memory available
to the ARM application processor is 1022MiB.
System-on-modules rely on an appropriate carrier board.
Testing of this PR has been done on the MBa8Xx carrier board
that is available from TQ Group as part of their starter kit.
To the best of my knowledge there is nothing in this PR
that depends on the carrier board itself; all code is SoM
specific and should support any carrier board.
Note: This support is very specifically for the TQMa8XQP configured
with 1GiB of memory.
This may be a starting point for supporting other boards that
also have the NXP i.MX 8QuadXPlus SoC (as well as the i.MX 8DXP
and possibly other SoC in the i.MX 8 family).
Support is limited to the specific SoM due to the way in which
platform support currently works for seL4. Building a kernel
currently relies on the information from the DTS file (which is
SoM + RAM configuration specific). It would be preferable to
allow more generic support but SoC families but that is beyond
the scope of this PR.
Signed-off-by: Ben Leslie <benno@brkawy.com>
This adds support for the ODroidC4. The ODroidC4 is just a beefier
ODroidC2 with some bits moved around. The devices we care about here are
all essentially the same except the cores are A55s instead of A53s.
Signed-off-by: Curtis Millar <curtis@curtism.me>
- Add underscored in name to improve readability.
- Add brackets to ensure parameters are atoms
- add comment clarifying c99 usage
Signed-off-by: Axel Heider <axelheider@gmx.de>
This adds a flags parameter to SchedControl_Configure to enable
configuration of a sporadic SC.
This also allows flags to be added in the future as needed without
breaking the API.
This allows the user to configure an SC either to be constrained as a
sporadic task where accumulated time is only delayed to when a task has
become runnable (implementing the sporadic server algorithm) or
whenever the task becomes the current executing task (implementing the
sliding-window constraint as in constant-bandwidth servers).
This can be used to prevent non-realtime tasks from exceeding bandwidth
under any circumstances, even in an over-committed configuration, whilst
also allowing work-conserving tasks to be configured in the same system.
To implement sporadic servers, we need to ensure that the suspension of
a task cannot be used as a mechanism to amplify budget of a task by
granting that task access to effectively multiple periods worth of
replenishments within a single period.
To align the implementation of SCs with the model of sporadic servers we
must delay available time until the release of a task. Within seL4, a
release would be any time where an SC changes from not being associated
with a Running, RunningVM, or Restart thread to one that is.
This can occur when an SC is bound to a new thread in such a state or
when a thread changes to such a state from any non-running states.
Critically, replenishments should not be delayed at the point when an SC
becomes the current SC (as was the case prior to this commit). This has
the effect of enforcing a continuous, constant bandwidth which is a
restriction that is incompatible with standard scheduling logic.
Accounting for this requires inserting a new refill_unblock_check
call whenever a sporadic SC is unblocked and removing the
refill_unblock_check call from when said SC is scheduled.
Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
define KernelPlatformZCU102 and KernelPlatformUltra96 that both
use KernelPlatformZynqmp then.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
This provides a generic way to print an seL4_Word on 32-bit and 64-bit
platforms, aligned with PRIu64 and friends. Use it as:
printf("foo = %" PRI_sel4_word "\n", (seL4_Word)foo);
Signed-off-by: Axel Heider <axelheider@gmx.de>
Today the file autoconf.h is created by the CMake build system and thus
HAVE_AUTOCONF is always defined. Time to get rid of some legacy by
removing the check if HAVE_AUTOCONF is set.
Signed-off-by: Axel Heider <axelheider@gmx.de>
This option was legacy from when autoconf.h wasn't always present in the
include path. Now it causes incorrect configuration options.
Signed-off-by: Kent McLeod <kent@kry10.com>
This symbol definition leads to an additional thread local storage
allocation for each object file that includes this header file. Then
when the final executable is linked, the weak symbol references are all
replaced by the global symbol declared by libsel4 in sel4_bootinfo.c.
The net result is unnecessarily large thread local storage being
required for each thread.
Signed-off-by: Kent McLeod <kent@kry10.com>
This makes the kernel configuration defaults public and known to the
user level. Generally shouldn't depend on these definitions outside of
code testing and benchmarking the kernel.
Signed-off-by: Curtis Millar <curtis@curtism.me>
A slot in the top level VSpace page table is used to hold the number of
SMMUv2 ContextBanks that are assigned to a VSpace. This means a
reduction of available virtual addresses at userlevel as the slot cannot
be used for holding regular mappings.
Signed-off-by: Kent McLeod <kent@kry10.com>
Remove unused cases and add break in switch statements.
Add conditions to sel4arch.xml.
Change guard in capdl printing to correct TK1_SMMU.
Set KernelArmSMMU default to off.
Add types to aarch32 syscall_stub_gen.py.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
- Add a chapter in the Hardware I/O Section
- Link API documentation back to chapter.
Co-authored-by: Qian Ge <Qian.Ge@data61.csiro.au>
Signed-off-by: Kent McLeod <kent@kry10.com>
Providing system calls on stream ID caps that unbinds its
context banks. Any future transaction using this stream ID
will result on faluts.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Providing a system call that removes an assigned vspace root from its
context bank. This operation causes the context bank being disabled
as it does not have a valid vspace root after the unassignment.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Providing system calls for conducting TLB invalidation operations
on all TLB entries or entries in a context bank.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Providing system calls that binds context banks to stream IDs.
Once the stream ID is bound, the transaction using that SID is
enabled.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Supporting user-level applications to assign vsapce root to context
banks through system calls. This commit also configures the context
bank according to stage 1 or stage 2 requirement.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Providing system calls on stream ID control cap and context bank
control cap for creating stream ID and context bank caps.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Adding the master control caps that are used to create transaction
and context banks caps. This commit includes the internal kernel
structure that required to manage any created transaction and
context bank caps.
Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
These files should have been released under BSD-2-Clause in the first
place (as per parent LICENSE.md file).
Closes#245
Signed-off-by: Gerwin Klein <gerwin.klein@data61.csiro.au>
With clang 11 these become bss symbols rather than commons, resulting in
multiple definition errors at link time. gcc 10 is likely to expose the
same issue.
Signed-off-by: Stefan O'Rear <sorear@fastmail.com>
- seL4_BenchmarkDumpAllThreadsUtilisation: Prints a JSON formatted
record of total and per-thread utilisation statistics about the system.
This currently includes a thread's total cycles scheduled, total number
of times scheduled, total cycles spent in the kernel and total number of
times entering the kernel and then totals of each for all threads on the
current core.
- seL4_BenchmarkResetAllThreadsUtilisation: Resets the current counts of
every user thread on the current core.
These syscalls are only available in a Debug build configuration as they
use a kernel debug list of all of the threads that exist for a given
node.
Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
For each thread also track number of times scheduled, number of kernel
entries and amount of cycles spent inside the kernel. Also add
core-wide totals for each.
Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
This register is visible to software executing at PL0 but not writeable.
Storing it in the VCPU context required custom save/restore handling as
it had to be explicitly handled when switching from a VCPU thread to a
non-VCPU thread so that it didn't become a channel. It is possible to
now update this register via seL4_TCB_WriteRegisters for software
executing at PL0.
This also fixes a bug where if a vcpu-thread is switched for a
non-vcpu-thread and then switched to a different vcpu-thread the
original vcpu-thread's copy of this register will get set to 0.
Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
This field is unused and is never set to anything by the kernel. Other
architecture definitions of seL4_UserException_Msg contain an equivalent
field for a current-program-status-register-like register that the fault
handler can read and modify as part of fault handling. RISC-V's
equivalent register SSTATUS doesn't contain any fields that would be
useful for a fault handler to modify at this stage and so the register
isn't transferred in the fault.
Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
This register is accessible from EL1 and affects whether Generic Timer
registers are accessible from EL0. When switching out of guests, the
kernel needs to restore the correct access for native threads.
Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
Introduced a new config flag to enable
userError format strings to be written to the IPC buffer.
Another config bool has been introduced to toggle
printing the error out and this can also be set at runtime.
Signed-off-by: Saer Debel <saer.debel@data61.csiro.au>
The format string in userError is now written to
the IPC buffer for debugging purposes.
This requires an snprintf which reuses vprintf with
a new structure for handling how output is done.
Signed-off-by: Saer Debel <saer.debel@data61.csiro.au>
This is the second commit for replacing ifndef with pargma
once in kernel header files. A few header files are missed
in the first round, hence this commit.
All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.
This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.
Added constant definitions for the VMPIDR (arm32) and VMPIDR_EL2
(arm64) registers. These being vcpu registers that can be
written, read, saved and restored. The 'Virtualization Multiprocessor
ID Register' (VMPIDR) is needed to program a vcpu's affinity during
initialisation. This is currently only exposed on SMP configurations.
Co-authored-by: Anna Lyons <anna@gh.st>
The PGD constants refer to the top level mapping object used by the
kernel for its own private mappings. Userlevel cannot create any PGD
objects and so these constants don't belong in libsel4.
Added support for reading and writing additional virtual timer
registers for vcpu hw read and write accesses. These include the
compare value register (CNTV_CVAL) and offset register (CNTV_OFF),
each represented as two 32 bit (high and low) registers on aarch32 and
as single 64 bit registers on aarch64.
Added support for explicitly saving and restoring the virtual
timer registers when the vcpu is enabled and disabled. This
ensures when the vcpu is switched in and out, the virtual timer
registers are restored to a state that is consistent to when
it was last run.
By default the CNTVOFF register will be updated by the kernel to
accumulate the time the VCPU is not running. From the guest this will
result in the VCNT register not increasing when the VCPU is suspended.
This behavior can be turned off by disabling the
KernelArmVtimerUpdateVOffset config option.
This commit introduces a new fault type, seL4_Fault_VPPIEvent.
This change means the kernel can reserve PPI interrupts and virtualise
them via delivering the irq to the active vcpu through a
specific fault. This enables multiplexing PPI IRQs across multiple VCPUS
which requires correctly masking and unmasking the IRQ depending on
which VCPU is running.
A new VCPU invocation, seL4_ARM_VCPU_AckVPPI is also added for
acknowledging the handling of the IRQ. This takes an IRQ as a parameter
but will only accept IRQ numbers that are sent as VPPIEvent faults.
Co-authored-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
For some reason the kernel documented and maintained constants for a
512MiB 'huge page' in riscv32 which is not part of the specification.
The references and constants are removed
Translation validation reports errors using the "real" struct type name
instead of the typedef name, so having anonymous structs makes debugging
translation validation harder.
Relates to #168. The definition for `seL4_UntypedRetypeMaxObjects` lives
in the UAPI `types.h` but appears to have no link to the value actually
used by the kernel, which is configurable. This change sets the UAPI
definition to the generated definition from the kernel config steps and
defaults to the previous fixed value if, for some reason, the configured
definition is not available.
- Remove Remap function from seL4 API for arm, x86, riscv and the
respective invocation implementation.
- Update Map as replacement for Remap
- Update manual
This allows a change of rights if the frame being mapped is already
mapped in at the given vaddr. To map a page to a different address,
unmap it first.
Co-authored-by: Hesham Almatary <hesham.almatary@data61.csiro.au>
Co-authored-by: Anna Lyons <Anna.Lyons@data61.csiro.au>
Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
This register is visible to software executing at EL0 but not writeable.
Storing it in the VCPU context required custom save/restore handling as
it had to be explicitly handled when switching from a VCPU thread to a
non-VCPU thread so that it didn't become a channel. It is possible to
now update this register via seL4_TCB_WriteRegisters for software
executing at EL0.
This also fixes a potential bug where if a vcpu-thread is switched for a
non-vcpu-thread and then switched to a different vcpu-thread the
original vcpu-thread's copy of this register will get set to 0.
Use the __ASSEMBLER__ macro to suppress C definitions from appearing in
non-C files when the preprocessor is used. Other libsel4/*/constants.h
files use this strategy to avoid duplicating definitions for seL4 object
sizes that can changed based on kernel configuration.
- seL4_TCB_Configure no longer takes a fault endpoint.
- seL4_TCB_SetSpace takes a cap in the callers cspace for the
fault endpoint, not the target tcbs.
- seL4_TCB_SetSchedParams now also takes a fault endpoint as above.
This change installs the fault endpoint cap into the tcb cnode
first validating it.
This means either of the functions that set it will now return an error
if the cap is not either a null cap or an endpoint with send and
grant rights.
Significantly, the cap passed to the function should be in the callers
cspace, not the target tcbs.
This allows users to define custom amounts of refills without
increasing the scheduling context size system wide.
also add libsel4 functions for refill size
This commit allows scheduling contexts to be bound
to notification objects. When a passive server
receives a notification it will receive the scheduling
context from the notification. When the server
blocks the scheduling context is returned.
This is the first part of the seL4 MCS. This commit:
* adds a scheduling context object. Threads without scheduling
context objects cannot be scheduled.
* replaces tcbTimeSlice with the scheduling context object
* adds seL4_SchedControl caps for each core
* adds seL4_SchedControl_Configure which allows users to configure
amount of ticks a scheduling context has, and set a core for the
scheduling context.
* adds seL4_SchedContext_Bind, Unbind and UnbindObject, which allows
a tcb to be bound to a scheduling context.
Update all scripts and build system to call python3, given python2's
upcoming doom. Use sys.maxsize instead of sys.maxint in one script
(maxint does not exist in python3).
This commit adds support for using a 40-bit physical addresses in
aarch64-hyp mode.
40-bit PA support is implemented by using a 3-stage translation, with a
13 bit page upper directory as the vspace root. PageGlobalDirectories
are not used in this configuration.
To use 40-bit PAs, platforms should set KernelArmPASizeBits40 to ON.
Co-authored-by: Yanyan Shen <yanyan.shen@data61.csiro.au>
Co-authored-by: Chris Guikema <chris.guikema@dornerworks.com>
Depending on the physical address range the top level translation table
may be a page upper directory or a page global directory. Rename in
libsel4 the invocations on top level structures to be on an
seL4_ARM_VSpace rather than an seL4_ARM_PageGlobalDirectory.
On aarch64-hyp the virtual address translation structure can differ
depending on the physical address range. This commit prepares to support
more than a single physical address range by removing the assumption
that the top-level structure in a vspace is a PGD, replacing it with the
concept of a vspace_root.
Specifically:
- add and use macros to refer to vtable bitfield generator functions
- use the existing vspace_root_t type rather than pgde_t
- pull performASIDPoolInvocation into header
- add and use VSPACE_PTR rather than PGDE_PTR
- rename decodeARMVPageGlobalDirectoryInvocation to refer to VSpace
- update comments/error messages
- rename variables
Created a new syscall, seL4_DebugSendIPI for ARM to send arbitrary SGIs
(software generated interrupts) to arbitrary cores. As SGIs are
specifically PPIs (private interrupts), this syscall effectively allows
to trigger PPIs on arbitrary cores, for debug/testing purposes.
Some platforms and configurations do not allow user code to change the
value of the register used for TLS. On these architectures a syscall can
be used to allow the kernel to update the register on their behalf.
This does not immediately update the value in the user context on many
configurations as the values are only stored in the user context on a
context switch.
Switched appropriate naming conventions.
Was using the aarch64, have switched to aarch64 names.
TIPDRURW -> tpidr_el0
TPIDRURO -> tpidrro_el0
TPIDRPRW -> tpidr_el1
Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so
that it can be written to from user-land.
Thread ID registers tpidr_el0 have been added to the user context for
aarch32 and aarch64.
Only the thread ID that is writeable from EL0 is saved in the TCB and
saved/restored on context switch.
Thread IDs that are only changed within a VM (the read-only thread ID
for exception level 0 and the thread ID for exception level 1) are
stored in the VCPU and saved and stored as part of VM enable/disable.
Thread IDs that are only changed with VMs have been separated out into
hypervisor code.
The globals frame no longer serves its original purpose of informing a
thread of its IPC buffer address, and instead as a virtual
implementation of thread ID registers.
TLS_BASE virtual register is replaced with FS_BASE and GS_BASE virtual
registers.
The FS_BASE and GS_BASE virtual registers are moved to the end of the
context so they need not be considered in the kernel exit and entry
implementation.
Removed tracking of ES, DS, FS, and GS segment selectors on kernel entry
and exit.
ES and DS are clobbered on kernel entry with the RPL 3 selector for a
DPL 3 linear data segment.
FS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with FS_BASE as the base. This is done on exit to reload the value from
the GDT.
GS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with GS_BASE as the base. This is done on exit to reload the value from
the GDT.
Kernel entry and exit code is refactored, simplified, and improved in
light of the above changes.
x64: update verified config to use fsgsbase instr
The verification platform for x64 relies on the fsgsbase instruction.
This removes the assumption that each platform sotres the IPC buffer
address in a platform-specific register. The IPC buffer address is
instead stored in a thread-local variable in libsel4 which must be
initialised by the runtime.
Prior to this change, seL4_MappingFailedLookupLevel() would retrun '22'
after any failed EPT mapping operation. This change fixes this to return
the correct amount of unresolved bits in the address.
